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-rw-r--r--src/VeriFuzz/Simulator/General.hs5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/VeriFuzz/Simulator/General.hs b/src/VeriFuzz/Simulator/General.hs
index 3615d3a..538ecaa 100644
--- a/src/VeriFuzz/Simulator/General.hs
+++ b/src/VeriFuzz/Simulator/General.hs
@@ -38,6 +38,11 @@ class (Simulator a) => Synthesize a where
-> FilePath -- ^ Output verilog file for the module
-> Sh () -- ^ does not return any values
+rootPath :: Sh FilePath
+rootPath = do
+ current <- pwd
+ maybe current fromText <$> get_env "VERIFUZZ_ROOT"
+
timeout :: FilePath -> [Text] -> Sh Text
timeout = command1 "timeout" ["180"] . toTextIgnore
{-# INLINE timeout #-}