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Diffstat (limited to 'src/VeriFuzz/Verilog/AST.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index f122214..ea7ef1b 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -209,6 +209,8 @@ data UnaryOperator = UnPlus -- ^ @+@ data Expr = Number {-# UNPACK #-} !BitVec -- ^ Number implementation containing the size and the value itself | Id {-# UNPACK #-} !Identifier + | VecSelect {-# UNPACK #-} !Identifier !Expr + | RangeSelect {-# UNPACK #-} !Identifier !Range -- ^ Symbols | Concat ![Expr] -- ^ Bit-wise concatenation of expressions represented by braces. |