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-rw-r--r--src/VeriFuzz/Verilog/AST.hs12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index 1b2cb19..b02da1b 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -104,6 +104,8 @@ module VeriFuzz.Verilog.AST
, declPort
, ModConn(..)
, modConn
+ , modConnName
+ , modExpr
)
where
@@ -398,11 +400,17 @@ instance QC.Arbitrary Port where
-- @
-- mod a(.y(y1), .x1(x11), .x2(x22));
-- @
-newtype ModConn = ModConn { _modConn :: Expr }
- deriving (Eq, Show, QC.Arbitrary)
+data ModConn = ModConn { _modConn :: Expr }
+ | ModConnNamed { _modConnName :: Identifier
+ , _modExpr :: Expr
+ }
+ deriving (Eq, Show)
makeLenses ''ModConn
+instance QC.Arbitrary ModConn where
+ arbitrary = ModConn <$> QC.arbitrary
+
data Assign = Assign { _assignReg :: LVal
, _assignDelay :: Maybe Delay
, _assignExpr :: Expr