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-rw-r--r--src/VeriFuzz/Verilog/BitVec.hs10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/VeriFuzz/Verilog/BitVec.hs b/src/VeriFuzz/Verilog/BitVec.hs
index 436af7b..cdae0f7 100644
--- a/src/VeriFuzz/Verilog/BitVec.hs
+++ b/src/VeriFuzz/Verilog/BitVec.hs
@@ -104,12 +104,12 @@ rotateBitVec b@(BitVec s _) n | n >= 0 = iterate rotateL1 b !! n
testBits a b' n' = if testBit n' a then bit b' else zeroBits
width' :: Integer -> Int
-width' a | a == 0 = 1
+width' a | a == 0 = 1
| otherwise = width'' a
- where
- width'' a' | a' == 0 = 0
- | a' == -1 = 1
- | otherwise = 1 + width'' (shiftR a' 1)
+ where
+ width'' a' | a' == 0 = 0
+ | a' == -1 = 1
+ | otherwise = 1 + width'' (shiftR a' 1)
both :: (a -> b) -> (a, a) -> (b, b)
both f (a, b) = (f a, f b)