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Diffstat (limited to 'src/Verismith/Circuit/Gen.hs')
| -rw-r--r-- | src/Verismith/Circuit/Gen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Verismith/Circuit/Gen.hs b/src/Verismith/Circuit/Gen.hs index 2d91ce8..c5cb697 100644 --- a/src/Verismith/Circuit/Gen.hs +++ b/src/Verismith/Circuit/Gen.hs @@ -2,7 +2,7 @@ Module : Verilog.Circuit.Gen Description : Generate verilog from circuit. Copyright : (c) 2019, Yann Herklotz Grave -License : GPLv3 +License : GPL-3 Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX |