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-rw-r--r--src/Verismith/Tool/QuartusLight.hs4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Verismith/Tool/QuartusLight.hs b/src/Verismith/Tool/QuartusLight.hs
index 86c9a3a..17f8570 100644
--- a/src/Verismith/Tool/QuartusLight.hs
+++ b/src/Verismith/Tool/QuartusLight.hs
@@ -59,8 +59,8 @@ runSynthQuartusLight sim (SourceInfo top src) = do
, "s/^module/(* multstyle = \"logic\" *) module/;"
, toTextIgnore inpf
]
- writefile quartusSdc $ "create_clock -period 5 -name clk [get_ports clock]"
- writefile quartusTcl $ quartusSynthConfig sim quartusSdc top inpf
+ writefile quartusSdc "create_clock -period 5 -name clk [get_ports clock]"
+ writefile quartusTcl $ quartusLightSynthConfig sim quartusSdc top inpf
ex (exec "quartus_sh") ["-t", toTextIgnore quartusTcl]
liftSh $ do
cp (fromText "simulation/vcs" </> fromText top <.> "vo")