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-rw-r--r--src/Verismith/Tool/Icarus.hs18
-rw-r--r--src/Verismith/Tool/Identity.hs2
-rw-r--r--src/Verismith/Tool/Internal.hs10
-rw-r--r--src/Verismith/Tool/Quartus.hs2
-rw-r--r--src/Verismith/Tool/QuartusLight.hs2
-rw-r--r--src/Verismith/Tool/Template.hs6
-rw-r--r--src/Verismith/Tool/Vivado.hs2
-rw-r--r--src/Verismith/Tool/XST.hs2
-rw-r--r--src/Verismith/Tool/Yosys.hs6
9 files changed, 25 insertions, 25 deletions
diff --git a/src/Verismith/Tool/Icarus.hs b/src/Verismith/Tool/Icarus.hs
index 4eb5a70..0fb2146 100644
--- a/src/Verismith/Tool/Icarus.hs
+++ b/src/Verismith/Tool/Icarus.hs
@@ -71,7 +71,7 @@ instance NFData Icarus where
defaultIcarus :: Icarus
defaultIcarus = Icarus "iverilog" "vvp"
-addDisplay :: [Statement] -> [Statement]
+addDisplay :: [Statement ann] -> [Statement ann]
addDisplay s = concat $ transpose
[ s
, replicate l $ TimeCtrl 1 Nothing
@@ -79,7 +79,7 @@ addDisplay s = concat $ transpose
]
where l = length s
-assignFunc :: [Port] -> ByteString -> Statement
+assignFunc :: [Port] -> ByteString -> Statement ann
assignFunc inp bs =
NonBlockAssign
. Assign conc Nothing
@@ -103,7 +103,7 @@ mask = T.replace "x" "0"
callback :: ByteString -> Text -> ByteString
callback b t = b <> convert (mask t)
-runSimIcarus :: Icarus -> SourceInfo -> [ByteString] -> ResultSh ByteString
+runSimIcarus :: Icarus -> (SourceInfo ann) -> [ByteString] -> ResultSh ByteString
runSimIcarus sim rinfo bss = do
let tb = ModDecl
"main"
@@ -134,7 +134,7 @@ runSimIcarusWithFile sim f _ = annotate (SimFail mempty) . liftSh $ do
fromBytes :: ByteString -> Integer
fromBytes = B.foldl' f 0 where f a b = a `shiftL` 8 .|. fromIntegral b
-tbModule :: [ByteString] -> ModDecl -> Verilog
+tbModule :: [ByteString] -> (ModDecl ann) -> (Verilog ann)
tbModule bss top =
Verilog [ instantiateMod top $ ModDecl "testbench" [] []
[ Initial
@@ -154,16 +154,16 @@ tbModule bss top =
where
inConcat = (RegConcat . filter (/= (Id "clk")) $ (Id . fromPort <$> (top ^. modInPorts)))
-counterTestBench :: CounterEg -> ModDecl -> Verilog
+counterTestBench :: CounterEg -> (ModDecl ann) -> (Verilog ann)
counterTestBench (CounterEg _ states) m = tbModule filtered m
where
filtered = convert . fold . fmap snd . filter ((/= "clk") . fst) <$> states
-runSimIc' :: (Synthesiser b) => ([ByteString] -> ModDecl -> Verilog)
+runSimIc' :: (Synthesiser b) => ([ByteString] -> (ModDecl ann) -> (Verilog ann))
-> FilePath
-> Icarus
-> b
- -> SourceInfo
+ -> (SourceInfo ann)
-> [ByteString]
-> Maybe ByteString
-> ResultSh ByteString
@@ -198,7 +198,7 @@ runSimIc :: (Synthesiser b)
=> FilePath -- ^ Data directory.
-> Icarus -- ^ Icarus simulator.
-> b -- ^ Synthesis tool to be tested.
- -> SourceInfo -- ^ Original generated program to test.
+ -> (SourceInfo ann) -- ^ Original generated program to test.
-> [ByteString] -- ^ Test vectors to be passed as inputs to the generated Verilog.
-> Maybe ByteString -- ^ What the correct output should be. If
-- 'Nothing' is passed, then just return 'Pass
@@ -207,5 +207,5 @@ runSimIc :: (Synthesiser b)
runSimIc = runSimIc' tbModule
runSimIcEC :: (Synthesiser b) => FilePath -> Icarus -> b
- -> SourceInfo -> CounterEg -> Maybe ByteString -> ResultSh ByteString
+ -> (SourceInfo ann) -> CounterEg -> Maybe ByteString -> ResultSh ByteString
runSimIcEC a b c d e = runSimIc' (const $ counterTestBench e) a b c d []
diff --git a/src/Verismith/Tool/Identity.hs b/src/Verismith/Tool/Identity.hs
index 93b05d5..9e436f3 100644
--- a/src/Verismith/Tool/Identity.hs
+++ b/src/Verismith/Tool/Identity.hs
@@ -44,7 +44,7 @@ instance Synthesiser Identity where
instance NFData Identity where
rnf = rwhnf
-runSynthIdentity :: Identity -> SourceInfo -> ResultSh ()
+runSynthIdentity :: Identity -> (SourceInfo ann) -> ResultSh ()
runSynthIdentity (Identity _ out) = writefile out . genSource
defaultIdentity :: Identity
diff --git a/src/Verismith/Tool/Internal.hs b/src/Verismith/Tool/Internal.hs
index 3336729..77ec4c9 100644
--- a/src/Verismith/Tool/Internal.hs
+++ b/src/Verismith/Tool/Internal.hs
@@ -66,7 +66,7 @@ class Tool a where
-- | Simulation type class.
class Tool a => Simulator a where
runSim :: a -- ^ Simulator instance
- -> SourceInfo -- ^ Run information
+ -> SourceInfo ann -- ^ Run information
-> [ByteString] -- ^ Inputs to simulate
-> ResultSh ByteString -- ^ Returns the value of the hash at the output of the testbench.
runSimWithFile :: a
@@ -100,12 +100,12 @@ instance Monoid Failed where
-- | Synthesiser type class.
class Tool a => Synthesiser a where
runSynth :: a -- ^ Synthesiser tool instance
- -> SourceInfo -- ^ Run information
+ -> SourceInfo ann -- ^ Run information
-> ResultSh () -- ^ does not return any values
synthOutput :: a -> FilePath
setSynthOutput :: a -> FilePath -> a
-renameSource :: (Synthesiser a) => a -> SourceInfo -> SourceInfo
+renameSource :: (Synthesiser a) => a -> SourceInfo ann -> SourceInfo ann
renameSource a src =
src & infoSrc . _Wrapped . traverse . modId . _Wrapped %~ (<> toText a)
@@ -129,7 +129,7 @@ checkPresent fp t = do
-- | Checks what modules are present in the synthesised output, as some modules
-- may have been inlined. This could be improved if the parser worked properly.
-checkPresentModules :: FilePath -> SourceInfo -> Sh [Text]
+checkPresentModules :: FilePath -> SourceInfo ann -> Sh [Text]
checkPresentModules fp (SourceInfo _ src) = do
vals <- forM (src ^.. _Wrapped . traverse . modId . _Wrapped)
$ checkPresent fp
@@ -146,7 +146,7 @@ replace fp t1 t2 = do
-- course, so instead this just searches and replaces all the module names. This
-- should find all the instantiations and definitions. This could again be made
-- much simpler if the parser works.
-replaceMods :: FilePath -> Text -> SourceInfo -> Sh ()
+replaceMods :: FilePath -> Text -> SourceInfo ann -> Sh ()
replaceMods fp t (SourceInfo _ src) =
void
. forM (src ^.. _Wrapped . traverse . modId . _Wrapped)
diff --git a/src/Verismith/Tool/Quartus.hs b/src/Verismith/Tool/Quartus.hs
index 128ad70..fd999ee 100644
--- a/src/Verismith/Tool/Quartus.hs
+++ b/src/Verismith/Tool/Quartus.hs
@@ -49,7 +49,7 @@ instance NFData Quartus where
defaultQuartus :: Quartus
defaultQuartus = Quartus Nothing "quartus" "syn_quartus.v"
-runSynthQuartus :: Quartus -> SourceInfo -> ResultSh ()
+runSynthQuartus :: Quartus -> (SourceInfo ann) -> ResultSh ()
runSynthQuartus sim (SourceInfo top src) = do
dir <- liftSh pwd
let ex = execute_ SynthFail dir "quartus"
diff --git a/src/Verismith/Tool/QuartusLight.hs b/src/Verismith/Tool/QuartusLight.hs
index 17f8570..881ef8e 100644
--- a/src/Verismith/Tool/QuartusLight.hs
+++ b/src/Verismith/Tool/QuartusLight.hs
@@ -49,7 +49,7 @@ instance NFData QuartusLight where
defaultQuartusLight :: QuartusLight
defaultQuartusLight = QuartusLight Nothing "quartus" "syn_quartus.v"
-runSynthQuartusLight :: QuartusLight -> SourceInfo -> ResultSh ()
+runSynthQuartusLight :: QuartusLight -> (SourceInfo ann) -> ResultSh ()
runSynthQuartusLight sim (SourceInfo top src) = do
dir <- liftSh pwd
let ex = execute_ SynthFail dir "quartus"
diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs
index ffa7240..ad9860c 100644
--- a/src/Verismith/Tool/Template.hs
+++ b/src/Verismith/Tool/Template.hs
@@ -61,7 +61,7 @@ write_verilog #{outputText a}
yosysSynthConfigStd :: Synthesiser a => a -> FilePath -> Text
yosysSynthConfigStd = yosysSynthConfig "synth"
-yosysSatConfig :: (Synthesiser a, Synthesiser b) => a -> b -> SourceInfo -> Text
+yosysSatConfig :: (Synthesiser a, Synthesiser b) => a -> b -> (SourceInfo ann) -> Text
yosysSatConfig sim1 sim2 (SourceInfo top src) = [st|read_verilog #{outputText sim1}
#{rename "_1" mis}
read_verilog syn_#{outputText sim2}.v
@@ -137,7 +137,7 @@ synth_design -part xc7k70t -top #{top}
write_verilog -force #{outf}
|]
-sbyConfig :: (Synthesiser a, Synthesiser b) => Maybe Text -> FilePath -> a -> b -> SourceInfo -> Text
+sbyConfig :: (Synthesiser a, Synthesiser b) => Maybe Text -> FilePath -> a -> b -> (SourceInfo ann) -> Text
sbyConfig mt datadir sim1 sim2 (SourceInfo top _) = [st|[options]
multiclock on
mode prove
@@ -169,7 +169,7 @@ top.v
<$> deps
readL = T.intercalate "\n" $ mappend "read -formal " <$> deps
-icarusTestbench :: (Synthesiser a) => FilePath -> Verilog -> a -> Text
+icarusTestbench :: (Synthesiser a) => FilePath -> (Verilog ann) -> a -> Text
icarusTestbench datadir t synth1 = [st|
`include "#{ddir}/data/cells_cmos.v"
`include "#{ddir}/data/cells_cyclone_v.v"
diff --git a/src/Verismith/Tool/Vivado.hs b/src/Verismith/Tool/Vivado.hs
index 272311e..e3d2538 100644
--- a/src/Verismith/Tool/Vivado.hs
+++ b/src/Verismith/Tool/Vivado.hs
@@ -49,7 +49,7 @@ instance NFData Vivado where
defaultVivado :: Vivado
defaultVivado = Vivado Nothing "vivado" "syn_vivado.v"
-runSynthVivado :: Vivado -> SourceInfo -> ResultSh ()
+runSynthVivado :: Vivado -> (SourceInfo ann) -> ResultSh ()
runSynthVivado sim (SourceInfo top src) = do
dir <- liftSh pwd
liftSh $ do
diff --git a/src/Verismith/Tool/XST.hs b/src/Verismith/Tool/XST.hs
index 5bc1438..4a4921c 100644
--- a/src/Verismith/Tool/XST.hs
+++ b/src/Verismith/Tool/XST.hs
@@ -52,7 +52,7 @@ instance NFData XST where
defaultXST :: XST
defaultXST = XST Nothing "xst" "syn_xst.v"
-runSynthXST :: XST -> SourceInfo -> ResultSh ()
+runSynthXST :: XST -> (SourceInfo ann) -> ResultSh ()
runSynthXST sim (SourceInfo top src) = do
dir <- liftSh pwd
let exec n = execute_
diff --git a/src/Verismith/Tool/Yosys.hs b/src/Verismith/Tool/Yosys.hs
index c87e697..3632f37 100644
--- a/src/Verismith/Tool/Yosys.hs
+++ b/src/Verismith/Tool/Yosys.hs
@@ -64,7 +64,7 @@ defaultYosys = Yosys Nothing "yosys" "syn_yosys.v"
yosysPath :: Yosys -> FilePath
yosysPath sim = maybe (S.fromText "yosys") (</> S.fromText "yosys") $ yosysBin sim
-runSynthYosys :: Yosys -> SourceInfo -> ResultSh ()
+runSynthYosys :: Yosys -> (SourceInfo ann) -> ResultSh ()
runSynthYosys sim (SourceInfo _ src) = do
dir <- liftSh $ do
dir' <- S.pwd
@@ -88,7 +88,7 @@ runEquivYosys
=> Yosys
-> a
-> b
- -> SourceInfo
+ -> (SourceInfo ann)
-> ResultSh ()
runEquivYosys yosys sim1 sim2 srcInfo = do
liftSh $ do
@@ -105,7 +105,7 @@ runEquivYosys yosys sim1 sim2 srcInfo = do
where checkFile = S.fromText [st|test.#{toText sim1}.#{toText sim2}.ys|]
runEquiv
- :: (Synthesiser a, Synthesiser b) => Maybe Text -> FilePath -> a -> b -> SourceInfo -> ResultSh ()
+ :: (Synthesiser a, Synthesiser b) => Maybe Text -> FilePath -> a -> b -> (SourceInfo ann) -> ResultSh ()
runEquiv mt datadir sim1 sim2 srcInfo = do
dir <- liftSh S.pwd
liftSh $ do
generated by cgit (git 2.34.1) at 2024-06-03 07:28:39 +0000