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-rw-r--r--src/Verismith/Verilog/Preprocess.hs2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/Verismith/Verilog/Preprocess.hs b/src/Verismith/Verilog/Preprocess.hs
index 909334b..56c3e2c 100644
--- a/src/Verismith/Verilog/Preprocess.hs
+++ b/src/Verismith/Verilog/Preprocess.hs
@@ -28,6 +28,7 @@ uncomment file = uncomment'
"" -> ""
'/' : '/' : rest -> " " ++ removeEOL rest
'/' : '*' : rest -> " " ++ remove rest
+ '(' : '*' : ')' : rest -> '(' : '*' : ')' : rest ++ remove rest
'(' : '*' : rest -> " " ++ remove rest
'"' : rest -> '"' : ignoreString rest
b : rest -> b : uncomment' rest
@@ -92,6 +93,7 @@ preprocess env file content =
"" : pp (head stack) (tail stack) env_ rest
| otherwise ->
error $ "`endif without associated `ifdef/`ifndef: " ++ file
+ "`timescale" : _ -> pp on stack env_ rest
_ -> (if on then ppLine env_ a else "") : pp on stack env_ rest
ppLine :: [(String, String)] -> String -> String