1 files changed, 18 insertions, 0 deletions
diff --git a/test/Reduce.hs b/test/Reduce.hs
index e6cc8ff..85a0654 100644
--- a/test/Reduce.hs
+++ b/test/Reduce.hs
@@ -261,6 +261,7 @@ activeWireTest = testCase "Active wires" $ do
   findActiveWires "top" verilog2 \\ ["x", "y", "z"] @?= []
   findActiveWires "top" verilog3 \\ ["x", "y", "clk", "r1", "r2"] @?= []
   findActiveWires "top" verilog4 \\ ["x", "y", "w", "a", "b"] @?= []
+  findActiveWires "top" verilog5 \\ ["r2", "r1", "x", "y"] @?= []
   where
     verilog1 =
       sourceInfo
@@ -339,6 +340,23 @@ module m2(y, z, x);
   output z;
 endmodule
 |]
+    verilog5 =
+      sourceInfo
+        "top"
+        [verilog|
+module top(y, x);
+  input x;
+  output y;
+  reg r1;
+  reg r2;
+  reg r3;
+  always @* begin
+    for (r1 = 1; r1 < 2; r1 = r1 + 1) begin
+      r2 <= 1'b0;
+    end
+  end
+endmodule
+|]
 
 halveStatementsTest :: TestTree
 halveStatementsTest = testCase "Statements" $ do