| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Extend property tests to ResultT | Yann Herklotz | 2019-04-17 | 1 | -25/+21 |
| * | Remove -Wall and -Werror, instead use --pedantic | Yann Herklotz | 2019-04-17 | 1 | -4/+1 |
| * | Add new Fuzzing technique, that checks simulators against each other | Yann Herklotz | 2019-04-17 | 1 | -11/+97 |
| * | Add Show instances to simulators | Yann Herklotz | 2019-04-17 | 5 | -8/+25 |
| * | Add '--pedantic' to travis | Yann Herklotz | 2019-04-17 | 1 | -3/+3 |
| * | Fix tests and remove Parser tests for now | Yann Herklotz | 2019-04-17 | 4 | -11/+65 |
| * | Fix other type errors and replace with Result type | Yann Herklotz | 2019-04-17 | 3 | -35/+49 |
| * | Update simulator with Result type | Yann Herklotz | 2019-04-17 | 5 | -61/+111 |
| * | Add Fuzzer and implement it with the result type | Yann Herklotz | 2019-04-17 | 1 | -35/+26 |
| * | Move Reduce file | Yann Herklotz | 2019-04-17 | 1 | -2/+2 |
| * | Add Result type | Yann Herklotz | 2019-04-17 | 1 | -0/+101 |
| * | Move declaration of SourceInfo | Yann Herklotz | 2019-04-15 | 13 | -37/+41 |
| * | Format with brittany and add right modules | Yann Herklotz | 2019-04-15 | 5 | -19/+20 |
| * | Remove non existant exports | Yann Herklotz | 2019-04-15 | 1 | -6/+1 |
| * | Fix warnings | Yann Herklotz | 2019-04-15 | 1 | -9/+14 |
| * | Rename Synthesisor -> Synthesiser | Yann Herklotz | 2019-04-15 | 5 | -13/+13 |
| * | Replace Env by Fuzz | Yann Herklotz | 2019-04-15 | 2 | -58/+113 |
| * | Some changes to recursion schemes | Yann Herklotz | 2019-04-14 | 1 | -18/+4 |
| * | Remove blocking assignment from Generation | Yann Herklotz | 2019-04-14 | 1 | -1/+1 |
| * | Change port declarations in Reduce | Yann Herklotz | 2019-04-14 | 1 | -4/+4 |
| * | Print out local time | Yann Herklotz | 2019-04-14 | 1 | -2/+5 |
| * | Add bit vector to Icarus simulation | Yann Herklotz | 2019-04-14 | 1 | -1/+6 |
| * | Add Bit vector instead of using numbers | Yann Herklotz | 2019-04-14 | 6 | -184/+142 |
| * | Changes to general types | Yann Herklotz | 2019-04-14 | 4 | -99/+90 |
| * | Update property tests | Yann Herklotz | 2019-04-14 | 1 | -18/+17 |
| * | Update cabal with added modules | Yann Herklotz | 2019-04-14 | 1 | -0/+6 |
| * | Add Eval module to evaluate expressions | Yann Herklotz | 2019-04-14 | 1 | -0/+103 |
| * | Add BitVec type to model Verilog bit vectors | Yann Herklotz | 2019-04-14 | 1 | -0/+115 |
| * | Add Quartus implementation | Yann Herklotz | 2019-04-14 | 1 | -0/+52 |
| * | Merge branch 'docs' | Yann Herklotz | 2019-04-13 | 2 | -0/+12 |
| |\ | |||||
| | * | Add partial documentation | Yann Herklotz | 2019-04-07 | 2 | -0/+12 |
| * | | Fix tests passing | Yann Herklotz | 2019-04-13 | 3 | -8/+6 |
| * | | Add recursion schemes implementation | Yann Herklotz | 2019-04-13 | 1 | -0/+84 |
| * | | Remove Arbitrary model | Yann Herklotz | 2019-04-12 | 2 | -227/+0 |
| * | | Add for loop to design | Yann Herklotz | 2019-04-12 | 4 | -46/+135 |
| * | | Change Port type to include lower bound | Yann Herklotz | 2019-04-12 | 6 | -25/+24 |
| * | | Fix the setup script for aws | Yann Herklotz | 2019-04-12 | 1 | -3/+3 |
| * | | Add vivado bugs | Yann Herklotz | 2019-04-12 | 5 | -0/+612 |
| * | | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 15 | -256/+351 |
| * | | Add probabilities to generation of expressions | Yann Herklotz | 2019-04-09 | 7 | -37/+51 |
| * | | Add generation of parameters and constant expressions | Yann Herklotz | 2019-04-09 | 3 | -22/+60 |
| * | | Add more configuration options | Yann Herklotz | 2019-04-09 | 1 | -31/+125 |
| * | | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 15 | -95/+204 |
| * | | Create Arbitrary module | Yann Herklotz | 2019-04-08 | 6 | -213/+235 |
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| * | Generate flip-flops instead of latches | Yann Herklotz | 2019-04-06 | 3 | -14/+5 |
| * | Fix setup script by mounting right drive | Yann Herklotz | 2019-04-06 | 1 | -1/+1 |
| * | Add more primitives to data/ | Yann Herklotz | 2019-04-06 | 2 | -7/+77 |
| * | Add dired locals to open verilog files | Yann Herklotz | 2019-04-06 | 1 | -0/+1 |
| * | New combine function | Yann Herklotz | 2019-04-04 | 1 | -0/+5 |
| * | Fix adding port to state and add everything to output | Yann Herklotz | 2019-04-04 | 1 | -8/+20 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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