| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add NonEmpty to tests | Yann Herklotz | 2019-05-13 | 4 | -27/+26 |
| * | Add Identity to Report | Yann Herklotz | 2019-05-13 | 2 | -23/+48 |
| * | Add reduction for the commandline | Yann Herklotz | 2019-05-13 | 2 | -43/+97 |
| * | Use NonEmpty to represent concatenation | Yann Herklotz | 2019-05-13 | 3 | -16/+16 |
| * | Change the arguments to Text in the Parser | Yann Herklotz | 2019-05-13 | 3 | -10/+31 |
| * | Add Identity synthesiser | Yann Herklotz | 2019-05-13 | 2 | -0/+45 |
| * | Remove modules that required $time | Yann Herklotz | 2019-05-12 | 1 | -310/+0 |
| * | Remove double inv | Yann Herklotz | 2019-05-12 | 1 | -10/+0 |
| * | Add BUF* to xilinx modules | Yann Herklotz | 2019-05-12 | 1 | -0/+963 |
| * | Add all the flip flops and latches | Yann Herklotz | 2019-05-12 | 1 | -114/+728 |
| * | Add FDE cell to xilinx | Yann Herklotz | 2019-05-12 | 1 | -0/+11 |
| * | Fix setup script for new aws | Yann Herklotz | 2019-05-12 | 1 | -3/+10 |
| * | Add randomisation of config file with --randomise | Yann Herklotz | 2019-05-12 | 2 | -6/+58 |
| * | Remove warnings | Yann Herklotz | 2019-05-12 | 1 | -118/+119 |
| * | Add more dependencies to build Yosys on EC2 | Yann Herklotz | 2019-05-12 | 3 | -12/+8 |
| * | Add defaultMain | Yann Herklotz | 2019-05-12 | 2 | -245/+245 |
| * | Add Quote.hs | Yann Herklotz | 2019-05-12 | 1 | -0/+49 |
| * | Add working statement reduction | Yann Herklotz | 2019-05-12 | 2 | -30/+145 |
| * | Implement module item reduction properly | Yann Herklotz | 2019-05-11 | 4 | -12/+24 |
| * | Fix warnings for CI | Yann Herklotz | 2019-05-11 | 2 | -5/+4 |
| * | Add reduction unit tests | Yann Herklotz | 2019-05-11 | 1 | -0/+2 |
| * | Add Plate instance to Statement | Yann Herklotz | 2019-05-11 | 1 | -0/+6 |
| * | Add Mutation class in Mutate.hs | Yann Herklotz | 2019-05-11 | 1 | -1/+99 |
| * | Add Quote export to main module | Yann Herklotz | 2019-05-11 | 1 | -0/+3 |
| * | Add new reduction techniques | Yann Herklotz | 2019-05-11 | 2 | -153/+232 |
| * | Fixed parser to parse all the generated verilog | Yann Herklotz | 2019-05-10 | 3 | -29/+129 |
| * | Add always and initial blocks to parser | Yann Herklotz | 2019-05-10 | 3 | -8/+157 |
| * | Fix some of the doctests in Mutate.hs | Yann Herklotz | 2019-05-10 | 1 | -5/+5 |
| * | Add constant expression to expression conversion and vice versa | Yann Herklotz | 2019-05-10 | 2 | -0/+23 |
| * | Fix but remove the doctests for now | Yann Herklotz | 2019-05-10 | 2 | -36/+38 |
| * | Add parser and reducer tests | Yann Herklotz | 2019-05-09 | 2 | -0/+106 |
| * | Add new pretty printer with indentation | Yann Herklotz | 2019-05-09 | 9 | -219/+191 |
| * | Add reduction strategy for modules | Yann Herklotz | 2019-05-09 | 5 | -16/+166 |
| * | Add NFData to force evaluation of config file | Yann Herklotz | 2019-05-09 | 10 | -167/+102 |
| * | Upgrade stack LTS version | Yann Herklotz | 2019-05-09 | 1 | -3/+3 |
| * | Add supported simulators to readme | Yann Herklotz | 2019-05-09 | 1 | -0/+2 |
| * | Fix unusable UNPACK | Yann Herklotz | 2019-05-09 | 1 | -1/+1 |
| * | Add combinational and sequential logic support | Yann Herklotz | 2019-05-09 | 3 | -97/+55 |
| * | Only show the seed | Yann Herklotz | 2019-05-07 | 1 | -3/+1 |
| * | Add configuration options for all simulators | Yann Herklotz | 2019-05-07 | 7 | -66/+213 |
| * | Add description field to Yosys | Yann Herklotz | 2019-05-07 | 3 | -14/+13 |
| * | Use abc for verification | Yann Herklotz | 2019-05-07 | 3 | -8/+6 |
| * | Create better command line output | Yann Herklotz | 2019-05-07 | 3 | -9/+16 |
| * | Rename some functions to use nicer names | Yann Herklotz | 2019-05-07 | 10 | -55/+62 |
| * | Add support for multiple modules | Yann Herklotz | 2019-05-07 | 4 | -11/+41 |
| * | Fix a warning in cells_cyclone_v.v | Yann Herklotz | 2019-05-06 | 1 | -241/+241 |
| * | Fix bug in Config.hs | Yann Herklotz | 2019-05-06 | 1 | -6/+6 |
| * | Replace by the unisims model | Yann Herklotz | 2019-05-06 | 1 | -13/+7 |
| * | [Fix #49] Add LDPE cell to xilinx | Yann Herklotz | 2019-05-06 | 1 | -24/+39 |
| * | Support multiple reg assigns in if statements | Yann Herklotz | 2019-05-06 | 10 | -82/+110 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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