| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add some more stats | Yann Herklotz | 2019-06-29 | 1 | -0/+3 |
| * | Add reported bugs | Yann Herklotz | 2019-06-29 | 1 | -8/+12 |
| * | Add found bugs | Yann Herklotz | 2019-06-29 | 1 | -0/+19 |
| * | Add back the simulation | Yann Herklotz | 2019-06-29 | 5 | -63/+60 |
| * | Add part of the simulator implementation | Yann Herklotz | 2019-06-29 | 3 | -5/+104 |
| * | Add exclude script | Yann Herklotz | 2019-06-06 | 1 | -0/+37 |
| * | Format all files | Yann Herklotz | 2019-06-05 | 10 | -104/+143 |
| * | Fix size in output wire | Yann Herklotz | 2019-06-05 | 1 | -2/+3 |
| * | Add combination option | Yann Herklotz | 2019-06-05 | 3 | -5/+10 |
| * | Add median and mean sampling | Yann Herklotz | 2019-06-02 | 1 | -10/+39 |
| * | Remove dead code | Yann Herklotz | 2019-06-02 | 1 | -1/+1 |
| * | Add selection for soup | Yann Herklotz | 2019-06-02 | 1 | -1/+1 |
| * | Add XOR to the output | Yann Herklotz | 2019-06-02 | 2 | -2/+3 |
| * | Add fix to synthesise correctly with Quartus without MAC | Yann Herklotz | 2019-06-02 | 1 | -1/+2 |
| * | Add check for quicker reduction | Yann Herklotz | 2019-06-02 | 1 | -17/+19 |
| * | Add extra experiments | Yann Herklotz | 2019-06-02 | 2 | -0/+66 |
| * | Fix cyclone_v cell declaration | Yann Herklotz | 2019-06-02 | 1 | -46/+12 |
| * | Add output | Yann Herklotz | 2019-05-30 | 1 | -3/+3 |
| * | Fix the conversion | Yann Herklotz | 2019-05-30 | 1 | -3/+13 |
| * | Add conversion script | Yann Herklotz | 2019-05-30 | 4 | -0/+21 |
| * | Add changes to swarm | Yann Herklotz | 2019-05-30 | 2 | -6/+23 |
| * | Add check for synthfails | Yann Herklotz | 2019-05-30 | 1 | -1/+2 |
| * | Add changes to work with older Vivado | Yann Herklotz | 2019-05-26 | 4 | -6/+6 |
| * | Fix reduction for statements | Yann Herklotz | 2019-05-25 | 4 | -15/+109 |
| * | Export helpers from Fuzz.hs | Yann Herklotz | 2019-05-25 | 1 | -0/+3 |
| * | Add more command line options for replay | Yann Herklotz | 2019-05-25 | 1 | -7/+69 |
| * | Use synthesiser instance | Yann Herklotz | 2019-05-25 | 1 | -1/+1 |
| * | Add synthesis fails to fuzzer | Yann Herklotz | 2019-05-25 | 2 | -0/+17 |
| * | Add reducesynthesis function | Yann Herklotz | 2019-05-25 | 1 | -0/+13 |
| * | Add timeout error to synthesisers | Yann Herklotz | 2019-05-25 | 2 | -12/+20 |
| * | Add scripts to run verifuzz | Yann Herklotz | 2019-05-25 | 2 | -0/+31 |
| * | Add more experiments | Yann Herklotz | 2019-05-25 | 4 | -0/+173 |
| * | No expression reduction | Yann Herklotz | 2019-05-24 | 1 | -1/+1 |
| * | Fix used wire check for clk | Yann Herklotz | 2019-05-24 | 4 | -14/+32 |
| * | Reduction throws away path if it finds a passing one | Yann Herklotz | 2019-05-24 | 2 | -21/+18 |
| * | Change parameters of generation | Yann Herklotz | 2019-05-22 | 1 | -7/+2 |
| * | Add extra large configuration | Yann Herklotz | 2019-05-22 | 1 | -0/+45 |
| * | Add hat sampling to config | Yann Herklotz | 2019-05-22 | 10 | -2/+22 |
| * | Add choice for hat sampling in config | Yann Herklotz | 2019-05-21 | 1 | -6/+14 |
| * | Add necessary exports to AST and CodeGen | Yann Herklotz | 2019-05-21 | 2 | -2/+2 |
| * | Add lines of code to report | Yann Herklotz | 2019-05-21 | 1 | -3/+11 |
| * | Add hat sampling | Yann Herklotz | 2019-05-21 | 1 | -18/+40 |
| * | Lower version bound on statitics | Yann Herklotz | 2019-05-21 | 1 | -1/+1 |
| * | Bump version with new changesv0.3.0.0 | Yann Herklotz | 2019-05-21 | 1 | -1/+1 |
| * | Add a different State and new FuzzReport output | Yann Herklotz | 2019-05-21 | 1 | -43/+112 |
| * | Add more fields to the FuzzReport | Yann Herklotz | 2019-05-21 | 1 | -34/+145 |
| * | Switch meaning of Semigroup | Yann Herklotz | 2019-05-21 | 1 | -1/+1 |
| * | Remove unused function | Yann Herklotz | 2019-05-21 | 1 | -3/+0 |
| * | Remove logging from within tools | Yann Herklotz | 2019-05-21 | 5 | -27/+9 |
| * | Add statistics | Yann Herklotz | 2019-05-21 | 1 | -0/+2 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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