| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Move verilog files into specific module | Yann Herklotz | 2018-12-28 | 1 | -207/+0 |
| * | Remove OverloadedStrings in favour of declaration in module | Yann Herklotz | 2018-12-27 | 1 | -2/+0 |
| * | Format fixes | Yann Herklotz | 2018-12-27 | 1 | -20/+20 |
| * | Add code generation for new types | Yann Herklotz | 2018-12-25 | 1 | -20/+130 |
| * | Fix documentation | Yann Herklotz | 2018-12-15 | 1 | -0/+24 |
| * | [Fix #1] Fix the negative number generation | Yann Herklotz | 2018-12-04 | 1 | -1/+4 |
| * | Fix typo | Yann Herklotz | 2018-12-01 | 1 | -1/+1 |
| * | Add newline after module declaration | Yann Herklotz | 2018-12-01 | 1 | -1/+1 |
| * | Fix the code generation | Yann Herklotz | 2018-12-01 | 1 | -1/+13 |
| * | Add more code generation for expressions | Yann Herklotz | 2018-12-01 | 1 | -0/+40 |
| * | Move generation to new location | Yann Herklotz | 2018-12-01 | 1 | -59/+16 |
| * | Add some simplifications (map -> fmap) | Yann Herklotz | 2018-11-29 | 1 | -5/+6 |
| * | Improve generation | Yann Herklotz | 2018-11-16 | 1 | -15/+15 |
| * | Basic generation with errors | Yann Herklotz | 2018-11-16 | 1 | -4/+22 |
| * | Add statements to the Verilog module | Yann Herklotz | 2018-11-16 | 1 | -12/+24 |
| * | Add style to the files | Yann Herklotz | 2018-11-14 | 1 | -4/+3 |
| * | Add testbench to the end | Yann Herklotz | 2018-11-09 | 1 | -1/+1 |
| * | Generate some Verilog code from graph | Yann Herklotz | 2018-11-09 | 1 | -0/+32 |
| * | Random generation of DAG | Yann Herklotz | 2018-11-09 | 1 | -1/+1 |
| * | Add initial module files | Yann Herklotz | 2018-11-09 | 1 | -0/+1 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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