| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Move verilog files into specific module | Yann Herklotz | 2018-12-28 | 1 | -80/+0 |
| * | Add instantiation function | Yann Herklotz | 2018-12-27 | 1 | -2/+7 |
| * | [Close #10, Fix #12] Add Mutations for wires | Yann Herklotz | 2018-12-25 | 1 | -7/+13 |
| * | Fix nesting, generation broken for nested groups | Yann Herklotz | 2018-12-23 | 1 | -3/+17 |
| * | Add nesting to the SourceText | Yann Herklotz | 2018-12-23 | 1 | -1/+16 |
| * | Start implementing the nesting functionality | Yann Herklotz | 2018-12-23 | 1 | -2/+23 |
| * | Add unimplemented nestId function | Yann Herklotz | 2018-12-22 | 1 | -0/+4 |
| * | Add Mutate module to VeriFuzz | Yann Herklotz | 2018-12-22 | 1 | -0/+15 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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