verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
*	Rename files out of the module	Yann Herklotz	2019-01-10	1	-461/+0
*	Rename module names so that I can move them	Yann Herklotz	2019-01-10	1	-72/+217
*	Add show instance to Identifier	Yann Herklotz	2019-01-09	1	-4/+8
*	Add num instance for the delay	Yann Herklotz	2019-01-02	1	-0/+9
*	Fix indentation	Yann Herklotz	2019-01-02	1	-10/+10
*	Remove Monoid instance for LVal, as it does not quite fit	Yann Herklotz	2019-01-01	1	-9/+0
*	Add monoid instance for LVal	Yann Herklotz	2019-01-01	1	-1/+10
*	Fix Monoid instance for Expr	Yann Herklotz	2019-01-01	1	-1/+1
*	Add back monoid instance for statement	Yann Herklotz	2019-01-01	1	-0/+3
*	Fix linting warnings	Yann Herklotz	2019-01-01	1	-1/+1
*	Formatting	Yann Herklotz	2019-01-01	1	-3/+3
*	Remove empty statement and Monoid instance	Yann Herklotz	2019-01-01	1	-4/+0
*	Fix Semigroup instances	Yann Herklotz	2019-01-01	1	-4/+8
*	Add string instance to expression	Yann Herklotz	2019-01-01	1	-12/+42
*	Add show instance and add concat to reglval	Yann Herklotz	2018-12-31	1	-29/+30
*	Large refactor	Yann Herklotz	2018-12-31	1	-240/+86
*	Finish module instantiation	Yann Herklotz	2018-12-31	1	-0/+6
*	Add direction to Decl and add doctest	Yann Herklotz	2018-12-31	1	-2/+4
*	Change modPort type from Maybe to List	Yann Herklotz	2018-12-30	1	-1/+1
*	[Fix #14] Add size to Port type	Yann Herklotz	2018-12-30	1	-6/+10
*	Make generation more controlled	Yann Herklotz	2018-12-29	1	-2/+4
*	Rearrange instances	Yann Herklotz	2018-12-29	1	-5/+5
*	Changes to the API	Yann Herklotz	2018-12-29	1	-13/+14
*	Fix documentation and copyright	Yann Herklotz	2018-12-28	1	-3/+3
*	Move verilog files into specific module	Yann Herklotz	2018-12-28	1	-0/+408