| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename files out of the module | Yann Herklotz | 2019-01-10 | 1 | -315/+0 |
| * | Rename module names so that I can move them | Yann Herklotz | 2019-01-10 | 1 | -11/+11 |
| * | Add conversion ByteString -> Integer | Yann Herklotz | 2019-01-02 | 1 | -3/+2 |
| * | Fix logic in CodeGen with maybe | Yann Herklotz | 2019-01-01 | 1 | -2/+4 |
| * | Fix linting warnings | Yann Herklotz | 2019-01-01 | 1 | -5/+5 |
| * | Add documentation | Yann Herklotz | 2019-01-01 | 1 | -0/+10 |
| * | Add missing case in function | Yann Herklotz | 2018-12-31 | 1 | -0/+2 |
| * | Add show instance and add concat to reglval | Yann Herklotz | 2018-12-31 | 1 | -10/+55 |
| * | Fix build errors | Yann Herklotz | 2018-12-31 | 1 | -0/+1 |
| * | Remove sep and fromList in favour of fold | Yann Herklotz | 2018-12-31 | 1 | -3/+3 |
| * | Large refactor | Yann Herklotz | 2018-12-31 | 1 | -58/+37 |
| * | Add direction to Decl and add doctest | Yann Herklotz | 2018-12-31 | 1 | -2/+3 |
| * | [Fix #17] Add size to ports | Yann Herklotz | 2018-12-31 | 1 | -3/+11 |
| * | [Fix #13, Fix #15] Fix type errors and add inst functions | Yann Herklotz | 2018-12-30 | 1 | -3/+3 |
| * | Fix verilog output for output port | Yann Herklotz | 2018-12-29 | 1 | -1/+1 |
| * | Changes to the API | Yann Herklotz | 2018-12-29 | 1 | -9/+14 |
| * | Fix documentation and copyright | Yann Herklotz | 2018-12-28 | 1 | -3/+3 |
| * | Move verilog files into specific module | Yann Herklotz | 2018-12-28 | 1 | -0/+263 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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