verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Large refactor with passing tests	Yann Herklotz	2019-04-02	1	-292/+0
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*	Rename to Verilog	Yann Herklotz	2019-04-02	1	-4/+4
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*	Make GenVerilog part of Arb	Yann Herklotz	2019-04-02	1	-3/+2
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*	Run through brittany	Yann Herklotz	2019-04-01	1	-37/+29
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*	Rewrite the parser with real lexer	Yann Herklotz	2019-03-31	1	-24/+21
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*	Useful renames and add if statement generation	Yann Herklotz	2019-03-30	1	-141/+143
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*	Change license name	Yann Herklotz	2019-03-30	1	-1/+1
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*	Add more probabilities to config	Yann Herklotz Grave	2019-03-06	1	-1/+1
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*	Rename Stmnt to Statement	Yann Herklotz Grave	2019-03-06	1	-16/+16
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*	Fix indentation	Yann Herklotz Grave	2019-03-01	1	-19/+22
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*	Reformat using brittany	Yann Herklotz Grave	2019-02-25	1	-15/+34
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*	Indent by 4	Yann Herklotz Grave	2019-02-17	1	-29/+29
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*	Brittany formatting	Yann Herklotz Grave	2019-02-17	1	-13/+14
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*	Fix CodeGen bug and add more property tests	Yann Herklotz Grave	2019-02-16	1	-1/+1
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*	Change Port type, adding signed info	Yann Herklotz Grave	2019-02-16	1	-4/+8
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*	Add export lists	Yann Herklotz Grave	2019-02-16	1	-17/+15
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*	Fix all warnings	Yann Herklotz Grave	2019-02-15	1	-1/+2
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*	Add brackets around number	Yann Herklotz	2019-02-02	1	-1/+1
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*	Fix imports	Yann Herklotz	2019-02-01	1	-10/+10
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*	More restructuring	Yann Herklotz	2019-02-01	1	-0/+276