verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
*	Add time and date by default	Yann Herklotz	2019-04-24	1	-3/+17
*	Add simulator support to the config file	Yann Herklotz	2019-04-23	1	-162/+46
*	Add helper functions to execute fuzzing multiple times	Yann Herklotz	2019-04-19	1	-9/+24
*	Fix compiling on CI	Yann Herklotz	2019-04-19	1	-0/+3
*	Equivalence test now running	Yann Herklotz	2019-04-19	1	-2/+1
*	Extend ResultT and Result with more instances	Yann Herklotz	2019-04-19	1	-5/+8
*	Add output information to Type	Yann Herklotz	2019-04-18	1	-44/+59
*	Add output path to each simulator	Yann Herklotz	2019-04-18	1	-37/+93
*	Add new Fuzzing technique, that checks simulators against each other	Yann Herklotz	2019-04-17	1	-11/+97
*	Add Fuzzer and implement it with the result type	Yann Herklotz	2019-04-17	1	-35/+26
*	Move declaration of SourceInfo	Yann Herklotz	2019-04-15	1	-2/+4
*	Format with brittany and add right modules	Yann Herklotz	2019-04-15	1	-1/+2
*	Fix warnings	Yann Herklotz	2019-04-15	1	-9/+14
*	Replace Env by Fuzz	Yann Herklotz	2019-04-15	1	-0/+113