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path: root/src/VeriFuzz/Verilog/CodeGen.hs
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* Large refactor with passing testsYann Herklotz2019-04-021-0/+293
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* More restructuringYann Herklotz2019-02-011-276/+0
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* [Fix #27] Add function to Expr and add Generation typeYann Herklotz2019-02-011-1/+17
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* [Fix #22] Fix SAT solver equivalence checkingYann Herklotz2019-01-201-1/+7
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* Prettify filesYann Herklotz2019-01-201-0/+2
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* Rename moduleId to modIdYann Herklotz2019-01-201-1/+1
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* Reformat with stylish-haskellYann Herklotz2019-01-191-8/+6
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* Add hlint changesYann Herklotz2019-01-191-1/+1
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* Set column to 100Yann Herklotz2019-01-191-33/+15
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* Add brittany formatting instead of stylish-haskellYann Herklotz2019-01-191-65/+63
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* Fix all the warningsYann Herklotz2019-01-101-27/+25
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* Fix warningsYann Herklotz2019-01-101-2/+2
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* Fix some importsYann Herklotz2019-01-101-53/+14
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* Rename files out of the moduleYann Herklotz2019-01-101-0/+315