diff options
| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 19:53:08 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 19:53:08 +0000 |
| commit | a27290529940e7a78dfe1d736447ca6f1cf72089 (patch) | |
| tree | 06c52149bbf2216fa02943dae0a4518749a372d0 /src/VeriFuzz/Verilog/CodeGen.hs | |
| parent | 75e6abdcb78c70b7449e5fd7f48d8a3e6b3d164b (diff) | |
| download | verismith-a27290529940e7a78dfe1d736447ca6f1cf72089.tar.gz verismith-a27290529940e7a78dfe1d736447ca6f1cf72089.zip | |
Add hlint changes
Diffstat (limited to 'src/VeriFuzz/Verilog/CodeGen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 34194a6..1551c1d 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -91,7 +91,7 @@ genModuleItem (ModInst (Identifier i) (Identifier name) conn) = i <> " " <> name <> "(" <> comma (genExpr . _modConn <$> conn) <> ")" <> ";\n" genModuleItem (Initial stat ) = "initial " <> genStmnt stat genModuleItem (Always stat ) = "always " <> genStmnt stat -genModuleItem (Decl dir port) = (maybe "" makePort dir) <> genPort port <> ";\n" +genModuleItem (Decl dir port) = maybe "" makePort dir <> genPort port <> ";\n" where makePort = (<> " ") . genPortDir -- | Generate continuous assignment |