verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
*	Fine tune the generation	Yann Herklotz	2019-04-23	1	-15/+13
*	Add event list generation for always blocks	Yann Herklotz	2019-04-23	1	-1/+2
*	Add support for more event lists	Yann Herklotz	2019-04-21	1	-1/+27
*	Reduce the wire size as Quartus was crashing	Yann Herklotz	2019-04-17	1	-1/+9
*	Move declaration of SourceInfo	Yann Herklotz	2019-04-15	1	-6/+7
*	Format with brittany and add right modules	Yann Herklotz	2019-04-15	1	-11/+11
*	Add Bit vector instead of using numbers	Yann Herklotz	2019-04-14	1	-58/+57
*	Fix tests passing	Yann Herklotz	2019-04-13	1	-1/+1
*	Add for loop to design	Yann Herklotz	2019-04-12	1	-32/+115
*	Fix the generation of modules and add initialisation	Yann Herklotz	2019-04-10	1	-50/+139
*	Add probabilities to generation of expressions	Yann Herklotz	2019-04-09	1	-19/+46
*	Add generation of parameters and constant expressions	Yann Herklotz	2019-04-09	1	-7/+47
*	Add Parameter type and remove Description	Yann Herklotz	2019-04-09	1	-3/+3
*	Create Arbitrary module	Yann Herklotz	2019-04-08	1	-0/+1
*	Generate flip-flops instead of latches	Yann Herklotz	2019-04-06	1	-11/+4
*	Fix adding port to state and add everything to output	Yann Herklotz	2019-04-04	1	-8/+20
*	Fix infinite loop in state based generation	Yann Herklotz	2019-04-03	1	-12/+17
*	Large refactor with passing tests	Yann Herklotz	2019-04-02	1	-0/+202