Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Add new maintainer email | Yann Herklotz | 2019-07-23 | 1 | -14/+11 |
* | Format files | Yann Herklotz | 2019-06-29 | 1 | -10/+13 |
* | Format with brittany | Yann Herklotz | 2019-05-13 | 1 | -55/+62 |
* | Change the arguments to Text in the Parser | Yann Herklotz | 2019-05-13 | 1 | -6/+26 |
* | Fixed parser to parse all the generated verilog | Yann Herklotz | 2019-05-10 | 1 | -13/+77 |
* | Add always and initial blocks to parser | Yann Herklotz | 2019-05-10 | 1 | -7/+118 |
* | Add Bit vector instead of using numbers | Yann Herklotz | 2019-04-14 | 1 | -16/+9 |
* | Change Port type to include lower bound | Yann Herklotz | 2019-04-12 | 1 | -1/+1 |
* | Fix the generation of modules and add initialisation | Yann Herklotz | 2019-04-10 | 1 | -3/+3 |
* | Add probabilities to generation of expressions | Yann Herklotz | 2019-04-09 | 1 | -1/+1 |
* | Add Parameter type and remove Description | Yann Herklotz | 2019-04-09 | 1 | -4/+2 |
* | Apply brittany to modified modules | Yann Herklotz | 2019-04-03 | 1 | -6/+8 |
* | Large refactor with passing tests | Yann Herklotz | 2019-04-02 | 1 | -0/+316 |