| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add option to drop reg and wire from output | Yann Herklotz | 2020-04-09 | 1 | -2/+24 |
| * | WIP changes to the AST types | Yann Herklotz | 2020-03-16 | 1 | -39/+39 |
| * | Update license notices | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 1 | -1/+1 |
| * | Add different identifier for forloops | Yann Herklotz | 2019-11-24 | 1 | -15/+17 |
| * | Add mtl dependency to enable easier use of transformers | Yann Herklotz | 2019-10-27 | 1 | -38/+32 |
| * | Add the literal list to the mod instantiation | Yann Herklotz | 2019-10-25 | 1 | -2/+3 |
| * | Fix subtle issue with module generation | Yann Herklotz | 2019-10-25 | 1 | -0/+1 |
| * | [Fix #63] Make build pass again | Yann Herklotz | 2019-10-06 | 1 | -48/+49 |
| * | Rename main modules | Yann Herklotz | 2019-09-18 | 1 | -0/+623 |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
| aboutsummaryrefslogtreecommitdiffstats |