verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Expand)	Author	Age	Files	Lines
*	Remove DRBG from Fuzz.hsfix/remove-DRBG	Yann Herklotz	2019-11-05	1	-13/+17
*	Add reduction pass to remove constants from concat	Yann Herklotz	2019-11-05	3	-4/+47
*	Add support for Quartus using projects	Yann Herklotz	2019-11-04	2	-17/+45
*	Add parsing of existing rtl when starting fuzz run	Yann Herklotz	2019-10-31	1	-8/+23
*	Add data-file installation path	Yann Herklotz	2019-10-29	5	-33/+42
*	Run simulation on all tools passing synthesis	Yann Herklotz	2019-10-28	1	-20/+27
*	Add --no-reduction	Yann Herklotz	2019-10-28	1	-21/+17
*	Add mtl dependency to enable easier use of transformers	Yann Herklotz	2019-10-27	2	-142/+172
*	Add OptParser to separate option parsing	Yann Herklotz	2019-10-27	1	-0/+266
*	Add comment to code generation	Yann Herklotz	2019-10-25	1	-1/+1
*	Add the literal list to the mod instantiation	Yann Herklotz	2019-10-25	1	-2/+3
*	Fix subtle issue with module generation	Yann Herklotz	2019-10-25	1	-0/+1
*	Change location of the html reports	Yann Herklotz	2019-10-18	2	-4/+6
*	Add -k functionality	Yann Herklotz	2019-10-18	2	-7/+29
*	Rename Sim to Tool	Yann Herklotz	2019-10-18	13	-65/+60
*	[Fix #63] Make build pass again	Yann Herklotz	2019-10-06	2	-57/+54
*	Rename main modules	Yann Herklotz	2019-09-18	33	-0/+7038