| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge branch 'master' into dev/reducerdev/reducer | Yann Herklotz | 2020-05-13 | 3 | -0/+215 |
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| | * | Add distance function (#75) | Yann Herklotz | 2020-05-09 | 3 | -49/+240 |
| * | | Fix generation of blocking assignment | Yann Herklotz | 2020-05-13 | 1 | -45/+129 |
| * | | Add for loops and events to reduction | Yann Herklotz | 2020-05-12 | 1 | -1/+18 |
| * | | Add line count to reduction | Yann Herklotz | 2020-05-12 | 1 | -3/+5 |
| * | | Remove single module instead of all | Yann Herklotz | 2020-05-12 | 1 | -25/+30 |
| * | | Change order of types in AST | Yann Herklotz | 2020-05-12 | 1 | -107/+107 |
| * | | Add debug to reduction | Yann Herklotz | 2020-05-12 | 2 | -4/+14 |
| * | | Format with ormolu | Yann Herklotz | 2020-05-12 | 37 | -4753/+5269 |
| * | | Tests passing for new reduction | Yann Herklotz | 2020-05-11 | 2 | -1/+13 |
| * | | Fix types with annotations | Yann Herklotz | 2020-05-11 | 13 | -44/+51 |
| * | | Add reduction annotations | Yann Herklotz | 2020-05-11 | 1 | -92/+134 |
| * | | Add proper annotation support | Yann Herklotz | 2020-05-11 | 1 | -69/+119 |
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| * | Add option to drop reg and wire from output | Yann Herklotz | 2020-04-09 | 3 | -18/+74 |
| * | Remove shakespeare dependency | Yann Herklotz | 2020-04-07 | 3 | -102/+103 |
| * | Remove statistic dependency | Yann Herklotz | 2020-04-07 | 1 | -3/+9 |
| * | Remove DRBG dependency | Yann Herklotz | 2020-04-07 | 3 | -31/+34 |
| * | Add annotations and make it compile again | Yann Herklotz | 2020-04-07 | 11 | -31/+41 |
| * | WIP changes to the AST types | Yann Herklotz | 2020-03-16 | 21 | -212/+210 |
| * | Changes to AST to support annotations | Yann Herklotz | 2020-03-04 | 1 | -289/+305 |
| * | Fix spacing in the generated Verilog | Yann Herklotz | 2020-03-03 | 1 | -16/+20 |
| * | Add case statement to the AST | Yann Herklotz | 2020-03-03 | 2 | -1/+41 |
| * | Update license notices | Yann Herklotz | 2020-01-06 | 35 | -35/+35 |
| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 35 | -35/+35 |
| * | Add correct cleaning function back | Yann Herklotz | 2019-12-26 | 1 | -1/+1 |
| * | Add configuration for default Yosys location | Yann Herklotz | 2019-12-26 | 3 | -7/+28 |
| * | Update documentation | Yann Herklotz | 2019-12-26 | 1 | -26/+49 |
| * | Add reduction stage back | Yann Herklotz | 2019-12-26 | 1 | -0/+1 |
| * | Add quartuslight | Yann Herklotz | 2019-12-10 | 1 | -2/+2 |
| * | Do not run counter example if no rerunner is specified | Yann Herklotz | 2019-12-03 | 7 | -26/+40 |
| * | Set aigsmt to none | Yann Herklotz | 2019-12-03 | 1 | -1/+1 |
| * | More minimisation | Yann Herklotz | 2019-12-03 | 1 | -3/+9 |
| * | Add different identifier for forloops | Yann Herklotz | 2019-11-24 | 1 | -15/+17 |
| * | Add ModConnNamed in testbench | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Add extension to simulation reduction | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Fix more changes to for loops | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Do not mutate the expression in the for loop | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Fix build | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Add output of v file during reduction | Yann Herklotz | 2019-11-24 | 2 | -35/+20 |
| * | Show the result as it is run | Yann Herklotz | 2019-11-24 | 1 | -4/+4 |
| * | Add cross-check between netlists | Yann Herklotz | 2019-11-24 | 3 | -11/+16 |
| * | Fix counter-example simulation run | Yann Herklotz | 2019-11-24 | 1 | -1/+1 |
| * | Support proper Quartus Pro version | Yann Herklotz | 2019-11-14 | 5 | -40/+166 |
| * | Add delay to finish | Yann Herklotz | 2019-11-14 | 1 | -1/+1 |
| * | Add z3 as default equivalence check with ABC | Yann Herklotz | 2019-11-14 | 1 | -0/+1 |
| * | Add reduction for simulation failures | Yann Herklotz | 2019-11-12 | 6 | -70/+174 |
| * | Use text to store counter-example | Yann Herklotz | 2019-11-12 | 1 | -15/+15 |
| * | Add counter example parsing | Yann Herklotz | 2019-11-10 | 7 | -47/+164 |
| * | Add reduction pass to remove constants from concat | Yann Herklotz | 2019-11-05 | 4 | -7/+57 |
| * | Add support for Quartus using projects | Yann Herklotz | 2019-11-04 | 2 | -17/+45 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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