Commit message (Expand) | Author | Age | Files | Lines | ||
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* | Add Mutate module to VeriFuzz | Yann Herklotz | 2018-12-22 | 2 | -0/+17 | |
* | Format ASTGen | Yann Herklotz | 2018-12-22 | 1 | -6/+3 | |
* | [Fix #2] Add generation of AST from Circuit | Yann Herklotz | 2018-12-22 | 4 | -19/+33 | |
* | Add shared code to code generation | Yann Herklotz | 2018-12-22 | 1 | -0/+34 | |
* | Add more functions to the code generation | Yann Herklotz | 2018-12-22 | 2 | -25/+21 | |
* | Add more AST generation | Yann Herklotz | 2018-12-20 | 1 | -1/+19 | |
* | Fix documentation | Yann Herklotz | 2018-12-15 | 5 | -15/+117 | |
* | Add new imports | Yann Herklotz | 2018-12-15 | 1 | -3/+5 | |
* | Add AST generation | Yann Herklotz | 2018-12-15 | 1 | -0/+47 | |
* | Rename types to circuit | Yann Herklotz | 2018-12-15 | 1 | -1/+15 | |
* | [Fix #1] Fix the negative number generation | Yann Herklotz | 2018-12-04 | 2 | -2/+5 | |
* | [Fix #8] Add Circuit newtype | Yann Herklotz | 2018-12-02 | 1 | -0/+3 | |
* | Fix typo | Yann Herklotz | 2018-12-01 | 1 | -1/+1 | |
* | Add newline after module declaration | Yann Herklotz | 2018-12-01 | 1 | -1/+1 | |
* | Fix the code generation | Yann Herklotz | 2018-12-01 | 1 | -1/+13 | |
* | Add all arbitrary instances and fix identifier | Yann Herklotz | 2018-12-01 | 1 | -15/+65 | |
* | Add more code to the shared code | Yann Herklotz | 2018-12-01 | 2 | -15/+15 | |
* | Add modport helper function | Yann Herklotz | 2018-12-01 | 1 | -0/+3 | |
* | Add more code generation for expressions | Yann Herklotz | 2018-12-01 | 1 | -0/+40 | |
* | Add missing modules to main library | Yann Herklotz | 2018-12-01 | 1 | -0/+2 | |
* | Add internal shared module | Yann Herklotz | 2018-12-01 | 1 | -0/+4 | |
* | Move generation to new location | Yann Herklotz | 2018-12-01 | 2 | -59/+79 | |
* | [lint] Remove unnecessary '$' | Yann Herklotz | 2018-12-01 | 1 | -1/+1 | |
* | Fix data types and apply more hlint suggestions | Yann Herklotz | 2018-12-01 | 1 | -8/+6 | |
* | Add helper methods | Yann Herklotz | 2018-12-01 | 1 | -6/+15 | |
* | Add assignment to ModuleItem | Yann Herklotz | 2018-11-30 | 1 | -3/+2 | |
* | Add more types | Yann Herklotz | 2018-11-30 | 1 | -12/+25 | |
* | Fix type issue in main | Yann Herklotz | 2018-11-30 | 1 | -5/+10 | |
* | Restructure and add tests | Yann Herklotz | 2018-11-30 | 1 | -19/+0 | |
* | Add lens library and extend types for AST | Yann Herklotz | 2018-11-30 | 1 | -5/+65 | |
* | Add AST to the exported modules | Yann Herklotz | 2018-11-30 | 1 | -0/+3 | |
* | Add some simplifications (map -> fmap) | Yann Herklotz | 2018-11-29 | 1 | -5/+6 | |
* | Add Verilog AST | Yann Herklotz | 2018-11-29 | 1 | -0/+13 | |
* | Improve generation | Yann Herklotz | 2018-11-16 | 1 | -15/+15 | |
* | Basic generation with errors | Yann Herklotz | 2018-11-16 | 3 | -6/+24 | |
* | Remove Nor and Nand from types | Yann Herklotz | 2018-11-16 | 1 | -4/+2 | |
* | Format and remove unnecessary declarations | Yann Herklotz | 2018-11-16 | 1 | -6/+3 | |
* | Add statements to the Verilog module | Yann Herklotz | 2018-11-16 | 1 | -12/+24 | |
* | Add style to the files | Yann Herklotz | 2018-11-14 | 5 | -24/+23 | |
* | Add testbench to the end | Yann Herklotz | 2018-11-09 | 1 | -1/+1 | |
* | Generate some Verilog code from graph | Yann Herklotz | 2018-11-09 | 2 | -9/+38 | |
* | Random generation of DAG | Yann Herklotz | 2018-11-09 | 4 | -34/+46 | |
* | Add main module | Yann Herklotz | 2018-11-09 | 1 | -0/+13 | |
* | Add initial module files | Yann Herklotz | 2018-11-09 | 3 | -0/+22 | |
* | Add simple verilog AND gate | Yann Herklotz | 2018-11-07 | 1 | -1/+1 | |
* | Generate random undirected graph | Yann Herklotz | 2018-11-05 | 1 | -29/+20 | |
* | Simple visualization | Yann Herklotz | 2018-10-29 | 1 | -18/+7 | |
* | Add case to make it more readable | Yann Herklotz | 2018-10-29 | 1 | -5/+10 | |
* | Partial tree visualization | Yann Herklotz | 2018-10-29 | 1 | -1/+2 | |
* | Broken change rendering the graph | Yann Herklotz | 2018-10-29 | 1 | -2/+16 |