| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix shuffle for VecSelect and RangeSelectHEADmaster | Yann Herklotz | 2021-07-30 | 1 | -1/+4 |
| * | Fix small bugs with the parser | Yann Herklotz | 2021-07-23 | 1 | -1/+1 |
| * | Add paranthesis | Yann Herklotz | 2021-07-23 | 1 | -1/+1 |
| * | Fix compilation issues | Yann Herklotz | 2021-07-23 | 2 | -6/+7 |
| * | Add command line variables | Yann Herklotz | 2021-07-23 | 3 | -2/+71 |
| * | Add shuffling of Verilog items | Yann Herklotz | 2021-07-14 | 1 | -0/+132 |
| * | Add changes to Icarus for fuzzing | Yann Herklotz | 2021-07-14 | 4 | -4/+41 |
| * | Add functions and fix EMI | Yann Herklotz | 2021-05-21 | 2 | -16/+51 |
| * | Add simulation support | Yann Herklotz | 2021-05-21 | 1 | -1/+1 |
| * | Fix top-level of interface | Yann Herklotz | 2021-05-21 | 2 | -3/+35 |
| * | Add new simulation for EMI | Yann Herklotz | 2021-05-19 | 2 | -22/+91 |
| * | Add showBS to Utils | Yann Herklotz | 2021-05-19 | 1 | -0/+9 |
| * | Add formal properties to AST | Yann Herklotz | 2021-05-19 | 2 | -0/+35 |
| * | Add Equivalence top-level generation | Yann Herklotz | 2021-05-19 | 1 | -5/+63 |
| * | Add more top-level changes | Yann Herklotz | 2021-05-19 | 3 | -32/+107 |
| * | Add top-level argument interface for EMI | Yann Herklotz | 2021-05-18 | 3 | -1/+98 |
| * | Add configuration for EMI testing | Yann Herklotz | 2021-05-18 | 2 | -11/+58 |
| * | Add full example of EMI testing | Yann Herklotz | 2021-05-17 | 2 | -2/+100 |
| * | Add EMI testing | Yann Herklotz | 2021-05-06 | 1 | -0/+11 |
| * | Fix parser for a larger set of inputs | Yann Herklotz | 2021-04-26 | 9 | -30/+71 |
| * | Save out of scope variables | Yann Herklotz | 2020-05-13 | 1 | -2/+8 |
| * | Remove removeDecl as that pass is already there | Yann Herklotz | 2020-05-13 | 1 | -1/+1 |
| * | Merge branch 'master' into dev/reducerdev/reducer | Yann Herklotz | 2020-05-13 | 3 | -0/+215 |
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| | * | Add distance function (#75) | Yann Herklotz | 2020-05-09 | 3 | -49/+240 |
| * | | Fix generation of blocking assignment | Yann Herklotz | 2020-05-13 | 1 | -45/+129 |
| * | | Add for loops and events to reduction | Yann Herklotz | 2020-05-12 | 1 | -1/+18 |
| * | | Add line count to reduction | Yann Herklotz | 2020-05-12 | 1 | -3/+5 |
| * | | Remove single module instead of all | Yann Herklotz | 2020-05-12 | 1 | -25/+30 |
| * | | Change order of types in AST | Yann Herklotz | 2020-05-12 | 1 | -107/+107 |
| * | | Add debug to reduction | Yann Herklotz | 2020-05-12 | 2 | -4/+14 |
| * | | Format with ormolu | Yann Herklotz | 2020-05-12 | 37 | -4753/+5269 |
| * | | Tests passing for new reduction | Yann Herklotz | 2020-05-11 | 2 | -1/+13 |
| * | | Fix types with annotations | Yann Herklotz | 2020-05-11 | 13 | -44/+51 |
| * | | Add reduction annotations | Yann Herklotz | 2020-05-11 | 1 | -92/+134 |
| * | | Add proper annotation support | Yann Herklotz | 2020-05-11 | 1 | -69/+119 |
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| * | Add option to drop reg and wire from output | Yann Herklotz | 2020-04-09 | 3 | -18/+74 |
| * | Remove shakespeare dependency | Yann Herklotz | 2020-04-07 | 3 | -102/+103 |
| * | Remove statistic dependency | Yann Herklotz | 2020-04-07 | 1 | -3/+9 |
| * | Remove DRBG dependency | Yann Herklotz | 2020-04-07 | 3 | -31/+34 |
| * | Add annotations and make it compile again | Yann Herklotz | 2020-04-07 | 11 | -31/+41 |
| * | WIP changes to the AST types | Yann Herklotz | 2020-03-16 | 21 | -212/+210 |
| * | Changes to AST to support annotations | Yann Herklotz | 2020-03-04 | 1 | -289/+305 |
| * | Fix spacing in the generated Verilog | Yann Herklotz | 2020-03-03 | 1 | -16/+20 |
| * | Add case statement to the AST | Yann Herklotz | 2020-03-03 | 2 | -1/+41 |
| * | Update license notices | Yann Herklotz | 2020-01-06 | 35 | -35/+35 |
| * | Update license to dual license GPLv3 | Yann Herklotz | 2020-01-06 | 35 | -35/+35 |
| * | Add correct cleaning function back | Yann Herklotz | 2019-12-26 | 1 | -1/+1 |
| * | Add configuration for default Yosys location | Yann Herklotz | 2019-12-26 | 3 | -7/+28 |
| * | Update documentation | Yann Herklotz | 2019-12-26 | 1 | -26/+49 |
| * | Add reduction stage back | Yann Herklotz | 2019-12-26 | 1 | -0/+1 |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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