verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add for loops and events to reduction	Yann Herklotz	2020-05-12	1	-0/+18
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*	Format with ormolu	Yann Herklotz	2020-05-12	1	-85/+198
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*	Tests passing for new reduction	Yann Herklotz	2020-05-11	1	-16/+23
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*	Fix the test suite	Yann Herklotz	2020-04-07	1	-32/+35
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*	Update license notices	Yann Herklotz	2020-01-06	1	-1/+1
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*	Update license to dual license GPLv3	Yann Herklotz	2020-01-06	1	-1/+1
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*	Add reduction pass to remove constants from concat	Yann Herklotz	2019-11-05	1	-8/+31
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*	Rename main modules	Yann Herklotz	2019-09-18	1	-2/+2
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*	Change name from VeriFuzz to VeriSmith	Yann Herklotz	2019-08-29	1	-2/+2
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*	Add new maintainer email	Yann Herklotz	2019-07-23	1	-2/+2
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*	Format files	Yann Herklotz	2019-06-29	1	-1/+1
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*	Fix reduction for statements	Yann Herklotz	2019-05-25	1	-0/+89
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*	Fix used wire check for clk	Yann Herklotz	2019-05-24	1	-0/+6
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*	Add test for removing unused wires	Yann Herklotz	2019-05-15	1	-0/+54
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*	Add test for clean all	Yann Herklotz	2019-05-14	1	-4/+67
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*	Add test for clean function	Yann Herklotz	2019-05-14	1	-6/+78
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*	Format with brittany	Yann Herklotz	2019-05-13	1	-7/+9
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*	Add more dependencies to build Yosys on EC2	Yann Herklotz	2019-05-12	1	-2/+2
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*	Add working statement reduction	Yann Herklotz	2019-05-12	1	-0/+85
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*	Implement module item reduction properly	Yann Herklotz	2019-05-11	1	-6/+6
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*	Fix warnings for CI	Yann Herklotz	2019-05-11	1	-2/+1
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*	Add new reduction techniques	Yann Herklotz	2019-05-11	1	-32/+139
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*	Add parser and reducer tests	Yann Herklotz	2019-05-09	1	-0/+50