.gitignore - verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

about summary refs log tree commit diff stats

path: root/.gitignore

blob: dc9bdd27b8869bb973a98c6083fc946813297d4d (plain)

# Files
TAGS
*.jou
*.log
*~
cabal.project.local
result

# Folders
.stack-work/
.shelly/
failed/
output*/
.ghc*/
dist*/
.direnv/