.gitignore - verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

about summary refs log tree commit diff stats

path: root/.gitignore

blob: 025b0e5bdea9339fbe7ae2a4e9caf254f5d20f9e (plain)

# Files
TAGS
*.jou
*.log
*~
cabal.project.local
result

# Folders
.stack-work
.shelly
failed
output*
.ghc*
dist*
.direnv