| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | .gitignore | 49 | logstatsplain |
| -rw-r--r-- | .hlint.yaml | 1764 | logstatsplain |
| -rw-r--r-- | .travis.yml | 613 | logstatsplain |
| -rw-r--r-- | LICENSE | 1531 | logstatsplain |
| -rw-r--r-- | README.md | 1431 | logstatsplain |
| -rw-r--r-- | Setup.hs | 56 | logstatsplain |
| d--------- | app | 35 | logstatsplain |
| d--------- | data | 172 | logstatsplain |
| d--------- | examples | 70 | logstatsplain |
| d--------- | report | 39 | logstatsplain |
| d--------- | src | 74 | logstatsplain |
| -rw-r--r-- | stack.yaml | 523 | logstatsplain |
| d--------- | test | 187 | logstatsplain |
| -rw-r--r-- | verifuzz.cabal | 3563 | logstatsplain |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
| aboutsummaryrefslogtreecommitdiffstats |