| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | .gitattributes | 63 | logstatsplain |
| -rw-r--r-- | .gitignore | 65 | logstatsplain |
| -rw-r--r-- | .travis.yml | 613 | logstatsplain |
| -rw-r--r-- | LICENSE | 1531 | logstatsplain |
| -rw-r--r-- | README.md | 1435 | logstatsplain |
| -rw-r--r-- | Setup.hs | 56 | logstatsplain |
| d--------- | app | 35 | logstatsplain |
| d--------- | bugs | 592 | logstatsplain |
| d--------- | data | 172 | logstatsplain |
| d--------- | examples | 109 | logstatsplain |
| d--------- | scripts | 36 | logstatsplain |
| d--------- | src | 74 | logstatsplain |
| -rw-r--r-- | stack.yaml | 533 | logstatsplain |
| d--------- | test | 187 | logstatsplain |
| -rw-r--r-- | verifuzz.cabal | 3929 | logstatsplain |
 |
index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
| aboutsummaryrefslogtreecommitdiffstats |