| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | .gitignore | 36 | logstatsplain |
| -rw-r--r-- | .travis.yml | 595 | logstatsplain |
| -rw-r--r-- | LICENSE | 1531 | logstatsplain |
| -rw-r--r-- | README.md | 495 | logstatsplain |
| -rw-r--r-- | Setup.hs | 56 | logstatsplain |
| d--------- | app | 71 | logstatsplain |
| d--------- | examples | 70 | logstatsplain |
| -rwxr-xr-x | run_sim.sh | 134 | logstatsplain |
| d--------- | src / Test | 31 | logstatsplain |
| -rw-r--r-- | stack.yaml | 59 | logstatsplain |
| d--------- | tests | 109 | logstatsplain |
| -rw-r--r-- | verifuzz.cabal | 2967 | logstatsplain |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
| aboutsummaryrefslogtreecommitdiffstats |