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| author | Yann Herklotz <git@yannherklotz.com> | 2021-09-11 09:56:44 +0100 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2021-09-11 09:56:44 +0100 |
| commit | 1a58aa8c63e160df12aa102f99e8d1cc9fb466a8 (patch) | |
| tree | 2dacd01dae4370ef108d273f126e70da232ba8e9 /content.org | |
| parent | dc3904239c3420313bda8c7a2bc07d7eb3963e04 (diff) | |
| download | yannherklotz.com-1a58aa8c63e160df12aa102f99e8d1cc9fb466a8.tar.gz yannherklotz.com-1a58aa8c63e160df12aa102f99e8d1cc9fb466a8.zip | |
Add draft
Diffstat (limited to 'content.org')
| -rw-r--r-- | content.org | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/content.org b/content.org index 777ce28..c5e13ef 100644 --- a/content.org +++ b/content.org @@ -34,7 +34,7 @@ to the input. If these differ, the design is automatically reduced until the bug Here you can find all my previous posts: -** Vericert :coq:hardware:FPGA:verilog: +** TODO Vericert :coq:hardware:FPGA:verilog: :PROPERTIES: :EXPORT_DATE: 2021-09-07 :EXPORT_FILE_NAME: 2021-09-07-vericert |