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| author | Yann Herklotz <git@yannherklotz.com> | 2021-09-10 19:52:06 +0100 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2021-09-10 19:52:06 +0100 |
| commit | 43d24c25e20afab8b7bc1370ded7f0ebc6c32ff2 (patch) | |
| tree | 486c09bb6fd2166067ceeabdef7939b0d74db586 /content.org | |
| parent | 06636e280046d8074eabb60e3b6f604032d85e70 (diff) | |
| download | yannherklotz.com-43d24c25e20afab8b7bc1370ded7f0ebc6c32ff2.tar.gz yannherklotz.com-43d24c25e20afab8b7bc1370ded7f0ebc6c32ff2.zip | |
Fix the content indentation
Diffstat (limited to 'content.org')
| -rw-r--r-- | content.org | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/content.org b/content.org index b64392f..aab3a32 100644 --- a/content.org +++ b/content.org @@ -10,11 +10,20 @@ #+HTML: <img src="/images/portrait.jpg" alt="Profile picture" class="profile-picture" /> #+HTML: <span class="first-letter">H</span> -i! I'm currently a first year PhD student in the Circuits and Systems group at Imperial College London, supervised by [John Wickerson](https://johnwickerson.github.io). - -My research focuses on formalising the process of converting high-level programming language descriptions to correct hardware that is functionally equivalent to the input. This process is called high-level synthesis (HLS), and allows software to be turned into custom accelerators automatically, which can then be placed on field-programmable gate arrays (FPGAs). An implementation in the [Coq](https://coq.inria.fr/) theorem prover called Vericert can be found on [Github](https://github.com/ymherklotz/vericert). - -I have also worked on random testing for FPGA synthesis tools. [Verismith](https://github.com/ymherklotz/verismith) is a fuzzer that will randomly generate a Verilog design, pass it to the synthesis tool, and use an equivalence check to compare the output to the input. If these differ, the design is automatically reduced until the bug is located. +i! I'm currently a first year PhD student in the Circuits and Systems group at Imperial College +London, supervised by [John Wickerson](https://johnwickerson.github.io). + +My research focuses on formalising the process of converting high-level programming language +descriptions to correct hardware that is functionally equivalent to the input. This process is +called high-level synthesis (HLS), and allows software to be turned into custom accelerators +automatically, which can then be placed on field-programmable gate arrays (FPGAs). An +implementation in the [Coq](https://coq.inria.fr/) theorem prover called Vericert can be found on +[Github](https://github.com/ymherklotz/vericert). + +I have also worked on random testing for FPGA synthesis +tools. [Verismith](https://github.com/ymherklotz/verismith) is a fuzzer that will randomly generate +a Verilog design, pass it to the synthesis tool, and use an equivalence check to compare the output +to the input. If these differ, the design is automatically reduced until the bug is located. * Blog ** Blog Index |