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| -rw-r--r-- | setup.org | 13 |
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diff --git a/content.org b/content.org index 8d6afb1..9e3b2e0 100644 --- a/content.org +++ b/content.org @@ -1,29 +1,28 @@ -#+title: Content -#+hugo_base_dir: ./ -#+hugo_section: ./ +#+title: Personal Document +#+author: Yann Herklotz +#+email: yann@yannherklotz.com +#+setupfile: setup.org * Yann Herklotz :PROPERTIES: :EXPORT_FILE_NAME: _index :END: -#+HTML: <img src="/images/portrait.jpg" alt="Profile picture" class="profile-picture" /> +#+html: <img src="/images/portrait.jpg" alt="Profile picture" class="profile-picture" /> -#+HTML: <span class="first-letter">H</span> -i! I'm currently a first year PhD student in the Circuits and Systems group at Imperial College -London, supervised by [John Wickerson](https://johnwickerson.github.io). +@@hugo:<span class="first-letter">H</span>@@@@latex:H@@i! I'm currently a first year PhD student in +the Circuits and Systems group at Imperial College London, supervised by [[https://johnwickerson.github.io][John Wickerson]]. My research focuses on formalising the process of converting high-level programming language descriptions to correct hardware that is functionally equivalent to the input. This process is called high-level synthesis (HLS), and allows software to be turned into custom accelerators automatically, which can then be placed on field-programmable gate arrays (FPGAs). An -implementation in the [Coq](https://coq.inria.fr/) theorem prover called Vericert can be found on -[Github](https://github.com/ymherklotz/vericert). +implementation in the [[https://coq.inria.fr/][Coq]] theorem prover called Vericert can be found on [[https://github.com/ymherklotz/vericert][Github]]. -I have also worked on random testing for FPGA synthesis -tools. [Verismith](https://github.com/ymherklotz/verismith) is a fuzzer that will randomly generate -a Verilog design, pass it to the synthesis tool, and use an equivalence check to compare the output -to the input. If these differ, the design is automatically reduced until the bug is located. +I have also worked on random testing for FPGA synthesis tools. [[https://github.com/ymherklotz/verismith][Verismith]] is a fuzzer that will +randomly generate a Verilog design, pass it to the synthesis tool, and use an equivalence check to +compare the output to the input. If these differ, the design is automatically reduced until the bug +is located. * Blog ** Blog Index @@ -136,7 +135,7 @@ to the note you want to insert. An example setup could be the following, which i three topics: (1) high-level synthesis (HLS), (2) computing and (3) verification. #+caption: The first step is to create a tree of notes in any hierarchy that seems to suit it best. Because of the numbering of the notes, other notes can always be inserted in between notes by adding a letter or number to the end. -[[/images/2020-12-20-zettelkasten-in-pure-org/zettelkasten-setup-1.png]] +{{{link([[/images/2020-12-20-zettelkasten-in-pure-org/zettelkasten-setup-1.png]],[[./static/images/2020-12-20-zettelkasten-in-pure-org/zettelkasten-setup-1.png]])}}} We can then add notes as shown above, adding them into the right category under a heading that makes the most sense, thereby building a tree. Each note is assigned a unique identifier (ID), which it @@ -151,7 +150,7 @@ diagram below that still has the general structure of the tree but also contains other notes that might be in a completely different topic but might still be generally relevant. #+caption: Once in a while, links to other notes in other categories or in the same category should be made. -[[/images/2020-12-20-zettelkasten-in-pure-org/zettelkasten-setup-2.png]] +{{{link([[/images/2020-12-20-zettelkasten-in-pure-org/zettelkasten-setup-2.png]],[[./static/images/2020-12-20-zettelkasten-in-pure-org/zettelkasten-setup-2.png]])}}} This allows for notes to be written anywhere that makes sense, but still connect to other areas in the notes that also might be relevant, thereby creating a network of relevant notes that might @@ -239,7 +238,7 @@ topic can then be created, for example, my topics are the following: A screenshot of how the top-level view of all my files looks like is shown in the screenshot below. #+caption: Example of the files containing the three topics I take notes in, displayed using the =columns= view in =org-mode=. -[[/images/2020-12-20-zettelkasten-in-pure-org/emacs-screenshot.jpg]] +{{{link([[/images/2020-12-20-zettelkasten-in-pure-org/emacs-screenshot.jpg]],[[./static/images/2020-12-20-zettelkasten-in-pure-org/emacs-screenshot.jpg]])}}} Next, we can keep adding notes to the respective files, and whenever we can see a possible link between two notes, we can add that to the relevant note. However, once in a while we have to take @@ -707,7 +706,7 @@ the glass using a femtosecond laser, which can then be read back using LEDs. The different properties such as angle and phase which dictate the current value at that location. #+caption: Project silica: image of 1978 "Superman" movie encoded on silica glass. Photo by Jonathan Banks for Microsoft. -[[/images/msr_research/project_silica.jpg]] +{{{link([[/images/msr_research/project_silica.jpg]],[[./static/images/msr_research/project_silica.jpg]])}}} **** [[https://www.microsoft.com/en-us/research/project/sirius/][Sirius]]: Optical Data Center Networks :PROPERTIES: @@ -1192,7 +1191,7 @@ This command line utility has to first be set up using a config file, which is u The most important parts to set up in the config file are -#+begin_src emacs-lisp +#+begin_src text IMAPAccount gmail Host imap.gmail.com User user@gmail.com @@ -1204,7 +1203,7 @@ The most important parts to set up in the config file are to setup the account, and then the following to setup the directories where it should download emails to -#+begin_src emacs-lisp +#+begin_src text IMAPStore gmail-remote Account gmail @@ -1340,18 +1339,15 @@ advantage of this is that the compiler does not have to be as clever anymore, as instructions that correspond directly with something that a programmer wants to do in the code, however, it means that the complexity of the hardware increases by a lot. -*** C to MIPS32 Compiler +** C to MIPS32 Compiler :PROPERTIES: :EXPORT_DATE: 2017-02-20 -:EXPORT_FILE_NAME: 2017-02-20-compiler +:EXPORT_FILE_NAME: compiler :EXPORT_HUGO_SECTION: blog -:CUSTOM_ID: cpu-introduction +:EXPORT_HUGO_CUSTOM_FRONT_MATTER: :summary "Implemented a C compiler to MIPS assembly code using flex and bison as the frontend. An abstract syntax tree is built from the parser and code generation is implemented as part of the AST." :aliases '(/blog/2017-02-20-compiler.html) +:CUSTOM_ID: compiler :END: -#+begin_summary -Implemented a C compiler to MIPS assembly code using flex and bison as the frontend. An abstract syntax tree is built from the parser and code generation is implemented as part of the AST. -#+end_summary - The compiler was made to translate C code to MIPS assembly. It was then tested using =qemu= and simulating the MIPS processor to run the binary. diff --git a/setup.org b/setup.org new file mode 100644 index 0000000..f4b5bb6 --- /dev/null +++ b/setup.org @@ -0,0 +1,13 @@ +#+hugo_base_dir: ./ +#+hugo_section: ./ + +#+begin_src emacs-lisp :exports results :results none +(setq org-export-babel-evaluate 'inline-only) + +(defun ymhg/link (arg1 arg2) + (cond + ((eq 'hugo org-export-current-backend) arg1) + (t arg2))) +#+end_src + +#+macro: link src_emacs-lisp[:results raw]{(ymhg/link "$1" "$2")} |