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-rw-r--r--papers_other.bib20
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+@inproceedings{OOPSLA '21,
+ author = {Herklotz, Yann and Pollard, James D. and Ramanathan, Nadesh and Wickerson, John},
+ title = {Formal Verification of High-Level Synthesis},
+ year = {2021},
+ number = {OOPSLA},
+ numpages = {30},
+ month = {11},
+ journal = {Proc. ACM Program. Lang.},
+ volume = {5},
+ publisher = {ACM},
+ doi = {10.1145/3485494},
+ url_manuscript = {/papers/oopsla21_fvhls.pdf},
+ url_slides = {/docs/oopsla21/slides_fvhls.pdf},
+ url_artifact = {https://github.com/ymherklotz/vericert},
+ url_video = {https://youtu.be/clPiKbKVlUA}
+}
+
+@inproceedings{FCCM '21,
+ author = {Herklotz, Yann and Du, Zewei and Ramanathan, Nadesh and Wickerson, John},
+ title = {An Empirical Study of the Reliability of High-Level Synthesis Tools},
+ year = {2021},
+ booktitle = {29th {IEEE} Annual Int. Symp. on Field-Programmable Custom Computing Machines},
+ keywords = {automated testing, compiler defect, compiler testing, random program generation, random testing},
+ numpages = 5,
+ doi = {10.1109/FCCM51124.2021.00034},
+ url_manuscript = {/papers/fccm21_esrhls.pdf},
+ url_artifact = {https://github.com/ymherklotz/fuzzing-hls},
+}
+
+@inproceedings{FPGA '20,
+ author = {Yann Herklotz and John Wickerson},
+ title = {Finding and Understanding Bugs in {FPGA} Synthesis Tools},
+ year = 2020,
+ booktitle = {ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays},
+ doi = {10.1145/3373087.3375310},
+ isbn = {978-1-4503-7099-8/20/02},
+ keywords = {automated testing, compiler defect, compiler testing, random program generation, random testing},
+ location = {Seaside, CA, USA},
+ numpages = 11,
+ url_poster = {/docs/msrphd2019/verismith_poster.pdf},
+ url_slides = {/docs/fpga2020/verismith_slides.pdf},
+ url_blog_post = {/blog/2019-06-19-verismith.html},
+ url_manuscript = {/papers/fpga20_fubfst.pdf},
+ url_artifact = {https://github.com/ymherklotz/verismith},
+}
diff --git a/papers_other.bib b/papers_other.bib
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+@inproceedings{LATTE '21,
+ author = {Herklotz, Yann and Wickerson, John},
+ title = {High-Level Synthesis Tools Should be Proven Correct},
+ year = {2021},
+ booktitle = {Workshop on Languages, Tools, and Techniques for Accelerator Design},
+ url_manuscript = {/papers/latte21_hlsspc.pdf},
+}
+
+@inproceedings{FPGA '21,
+ author = {Du, Zewei and Herklotz, Yann and Ramanathan, Nadesh and Wickerson, John},
+ title = {Fuzzing High-Level Synthesis Tools},
+ year = {2021},
+ isbn = {9781450382182},
+ doi = {10.1145/3431920.3439466},
+ abstract = {High-level synthesis (HLS) is becoming an increasingly important part of the computing landscape, even in safety-critical domains where correctness is key. As such, HLS tools are increasingly relied upon. But are they trustworthy?We have subjected three widely used HLS tools - LegUp, Xilinx Vivado HLS, and the Intel HLS Compiler - to a rigorous fuzzing campaign using thousands of random, valid C programs that we generated using a modified version of the Csmith tool. For each C program, we compiled it to a hardware design using the HLS tool under test and checked whether that hardware design generates the same output as an executable generated by the GCC compiler. When discrepancies arose between GCC and the HLS tool under test, we reduced the C program to a minimal example in order to zero in on the potential bug. Our testing campaign has revealed that all three HLS tools can be made either to crash or to generate wrong code when given valid C programs, and thereby underlines the need for these increasingly trusted tools to be more rigorously engineered. Out of 6700 test cases, we found 272 programs that failed in at least one tool, out of which we were able to discern at least 6 unique bugs.},
+ booktitle = {ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays},
+ keywords = {fuzzing, high-level synthesis, C++, C},
+ location = {Virtual Event, USA},
+ url_slides = {/docs/fpga2021/fpga2021_slides.pdf},
+}