Add content

1 files changed, 24 insertions, 0 deletions

diff --git a/content/zettel/1b9c.md b/content/zettel/1b9c.md
new file mode 100644
index 0000000..869414c
--- /dev/null
+++ b/content/zettel/1b9c.md
@@ -0,0 +1,24 @@
++++
+title = "Negative Edge Triggered RAM"
+date = "2022-06-28"
+author = "Yann Herklotz"
+tags = []
+categories = []
+backlinks = ["1b9b"]
+forwardlinks = ["1c2", "1b8"]
+zettelid = "1b9c"
++++
+
+Currently Vericert triggers at the negative edge of an always block.
+This means that loads and stores take 2 and 1 clock cycle respectively,
+and simplifies the proof. It does mean though that only half the time is
+available for logic. Instead, it would be better to actually have 2 and
+3 clock cycles for stores and loads, especially when hyperblock
+scheduling ([\#1c2], [\#1b8]) is supported.
+
+I guess that negative edge triggered RAMs are supported in most
+synthesis tools, however, only insofar as them turning it into a
+positive edge triggered RAM and then halving the period.
+
+  [\#1c2]: /zettel/1c2
+  [\#1b8]: /zettel/1b8