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+title = "Optimisations"
+author = "Yann Herklotz"
+tags = []
+categories = []
+backlinks = ["2b1", "1b"]
+forwardlinks = ["1c1", "1c2", "1c3", "1c4", "1c5", "1c7", "1c6", "1c8", "1d"]
+zettelid = "1c"
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+
+The survey by Nane et al. \[1\] goes over some of the optimsations that
+are present in high-level synthesis tools, and that are important to
+make them efficient and usable.
+
+Some of the optimisations are
+
+-   scheduling ([\#1c1], [\#1c2], [\#1c3]),
+-   operation chaining ([\#1c4]),
+-   register allocation ([\#1c5]),
+-   bitwidth analysis and optimisation,
+-   memory space allocation,
+-   loop optimisations: polyhedral analysis ([\#1c7]),
+-   hardware resource library,
+-   speculation and code motion: loop pipelining ([\#1c6]),
+-   exploiting spatial parallelism, and
+-   if-conversion ([\#1c8]).
+
+<div id="refs" class="references csl-bib-body" markdown="1">
+
+<div id="ref-nane16_survey_evaluat_fpga_high_level_synth_tools"
+class="csl-entry" markdown="1">
+
+<span class="csl-left-margin">\[1\]
+</span><span class="csl-right-inline">R. Nane *et al.*, “A survey and
+evaluation of fpga high-level synthesis tools,” *IEEE Transactions on
+Computer-Aided Design of Integrated Circuits and Systems*, vol. 35, no.
+10, pp. 1591–1604, Oct. 2016, doi: [10.1109/TCAD.2015.2513673].</span>
+
+</div>
+
+</div>
+
+  [\#1c1]: /zettel/1c1
+  [\#1c2]: /zettel/1c2
+  [\#1c3]: /zettel/1c3
+  [\#1c4]: /zettel/1c4
+  [\#1c5]: /zettel/1c5
+  [\#1c7]: /zettel/1c7
+  [\#1c6]: /zettel/1c6
+  [\#1c8]: /zettel/1c8
+  [10.1109/TCAD.2015.2513673]: https://doi.org/10.1109/TCAD.2015.2513673