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diff --git a/content/zettel/1c2a2b.md b/content/zettel/1c2a2b.md new file mode 100644 index 0000000..b686c93 --- /dev/null +++ b/content/zettel/1c2a2b.md @@ -0,0 +1,28 @@ ++++ +title = "Timing constraints" +author = "Yann Herklotz" +tags = [] +categories = [] +backlinks = ["1c2a2a"] +forwardlinks = ["3c3", "1c2a2c"] +zettelid = "1c2a2b" ++++ + +Relative timing constraints + +: These are relative timing constraints for IO interaction, which is + probably not that needed for Vericert ([\#3c3]). For example, these + can be used to have a specific amount of cycles in between + operations. + +Latency constraint + +: This is used to specify the maximum latency for a subgraph in the + CDFG. Not sure when this would be useful in practice. + +Cycle time constraint +: This is to limit the maximum combinational delay within a clock + cycle. This will basically implement operation chaining as long as + the operations take less time than the maximum combinational delay. + + [\#3c3]: /zettel/3c3 |