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diff --git a/content/zettel/1c6a1.md b/content/zettel/1c6a1.md new file mode 100644 index 0000000..326712f --- /dev/null +++ b/content/zettel/1c6a1.md @@ -0,0 +1,21 @@ ++++ +title = "Implementation of a Hardware Pipeline" +author = "Yann Herklotz" +tags = [] +categories = [] +backlinks = ["1c6a"] +forwardlinks = ["1c6a2"] +zettelid = "1c6a1" ++++ + +A hardware pipeline can be directly inferred from the schedule that is +output by the modulo scheduling algorithm. This can be done by taking +the amounts of states, and generating a state machine inside of that +pipeline that will go from one state to the other. A controller can then +be added to handle the loop iterator and feed the pipeline with the +correct II. + +However, this can also be handled inside of the pipeline itself, by +using the `ready` and `valid` signals. When the pipeline is in a state +that it can't accept another input in, then the `ready` signal is set to +0. |