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+title = "The global valid signal"
+author = "Yann Herklotz"
+tags = []
+categories = []
+backlinks = ["5a2"]
+forwardlinks = ["5a2b"]
+zettelid = "5a2a"
++++
+
+This is the simplest way to design pipelined hardware, and can be useful
+for one important scenario, when the rate of the input data is constant.
+This allows the enable signal to be asserted at the rate at which new
+data will enter the pipeline, therefore advancing the data to the next
+stage. The logic for a pipeline stage using a global enable looks
+something like the following:
+
+``` verilog
+always @(posedge clk) if (CE) out <= $compute(in);
+```
+
+One main use-case of such an application is DSP, as signals will come in
+and exit a the rate that the ADC or DAC is sampling at.