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author | Yann Herklotz <ymherklotz@gmail.com> | 2017-02-19 23:17:47 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2017-02-19 23:17:47 +0000 |
commit | 557fd604e7c9a079d136c76089446d9c714438ec (patch) | |
tree | b96a0953749ee5839bf109a0f5595fb4e9243337 /led.syr | |
download | FPGA_Playground-557fd604e7c9a079d136c76089446d9c714438ec.tar.gz FPGA_Playground-557fd604e7c9a079d136c76089446d9c714438ec.zip |
Adding initial files
Diffstat (limited to 'led.syr')
-rw-r--r-- | led.syr | 128 |
1 files changed, 128 insertions, 0 deletions
@@ -0,0 +1,128 @@ +Release 14.7 - xst P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.03 secs + +--> +Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.03 secs + +--> +Reading design: led.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) Partition Resource Summary + 9.3) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "led.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "led" +Output Format : NGC +Target Device : xc3s250e-4-vq100 + +---- Source Options +Top Module Name : led +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : Yes +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : Yes +Resource Sharing : YES +Asynchronous To Synchronous : NO +Multiplier Style : Auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 24 +Register Duplication : YES +Slice Packing : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Yes +Use Synchronous Set : Yes +Use Synchronous Reset : Yes +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +Verilog 2001 : YES +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling verilog file "led.v" in library work +Module <led> compiled +No errors in compilation +Analysis of file <"led.prj"> succeeded. + + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +ERROR:Xst - "led.v" line 21: Module <led> has no port. +--> + + +Total memory usage is 497212 kilobytes + +Number of errors : 1 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + |