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| author | Yann Herklotz <ymherklotz@gmail.com> | 2017-02-19 23:17:47 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2017-02-19 23:17:47 +0000 |
| commit | 557fd604e7c9a079d136c76089446d9c714438ec (patch) | |
| tree | b96a0953749ee5839bf109a0f5595fb4e9243337 /led_envsettings.html | |
| download | FPGA_Playground-557fd604e7c9a079d136c76089446d9c714438ec.tar.gz FPGA_Playground-557fd604e7c9a079d136c76089446d9c714438ec.zip | |
Adding initial files
Diffstat (limited to 'led_envsettings.html')
| -rw-r--r-- | led_envsettings.html | 382 |
1 files changed, 382 insertions, 0 deletions
diff --git a/led_envsettings.html b/led_envsettings.html new file mode 100644 index 0000000..215f634 --- /dev/null +++ b/led_envsettings.html @@ -0,0 +1,382 @@ +<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD> +<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> +<center><big><big><b>System Settings</b></big></big></center><br> +<A NAME="Environment Settings"></A> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD> +</tr> +<tr bgcolor='#ffff99'> +<td><b>Environment Variable</b></td> +<td><b>xst</b></td> +<td><b>ngdbuild</b></td> +<td><b>map</b></td> +<td><b>par</b></td> +</tr> +<tr> +<td>LD_LIBRARY_PATH</td> +<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>PATH</td> +<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/local/sbin:<br>/usr/local/bin:<br>/usr/bin:<br>/usr/lib/jvm/default/bin:<br>/usr/bin/site_perl:<br>/usr/bin/vendor_perl:<br>/usr/bin/core_perl</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>XILINX</td> +<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>XILINX_DSP</td> +<td>/opt/Xilinx/14.7/ISE_DS/ISE</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>XILINX_EDK</td> +<td>/opt/Xilinx/14.7/ISE_DS/EDK</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>XILINX_PLANAHEAD</td> +<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +</TABLE> +<A NAME="Synthesis Property Settings"></A> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD> +</tr> +<tr bgcolor='#ffff99'> +<td><b>Switch Name</b></td> +<td><b>Property Name</b></td> +<td><b>Value</b></td> +<td><b>Default Value</b></td> +</tr> +<tr> +<td>-ifn</td> +<td> </td> +<td>led.prj</td> +<td> </td> +</tr> +<tr> +<td>-ifmt</td> +<td> </td> +<td>mixed</td> +<td>MIXED</td> +</tr> +<tr> +<td>-ofn</td> +<td> </td> +<td>led</td> +<td> </td> +</tr> +<tr> +<td>-ofmt</td> +<td> </td> +<td>NGC</td> +<td>NGC</td> +</tr> +<tr> +<td>-p</td> +<td> </td> +<td>xc3s250e-4-vq100</td> +<td> </td> +</tr> +<tr> +<td>-top</td> +<td> </td> +<td>led</td> +<td> </td> +</tr> +<tr> +<td>-opt_mode</td> +<td>Optimization Goal</td> +<td>Speed</td> +<td>SPEED</td> +</tr> +<tr> +<td>-opt_level</td> +<td>Optimization Effort</td> +<td>1</td> +<td>1</td> +</tr> +<tr> +<td>-iuc</td> +<td>Use synthesis Constraints File</td> +<td>NO</td> +<td>NO</td> +</tr> +<tr> +<td>-keep_hierarchy</td> +<td>Keep Hierarchy</td> +<td>No</td> +<td>NO</td> +</tr> +<tr> +<td>-netlist_hierarchy</td> +<td>Netlist Hierarchy</td> +<td>As_Optimized</td> +<td>as_optimized</td> +</tr> +<tr> +<td>-rtlview</td> +<td>Generate RTL Schematic</td> +<td>Yes</td> +<td>NO</td> +</tr> +<tr> +<td>-glob_opt</td> +<td>Global Optimization Goal</td> +<td>AllClockNets</td> +<td>ALLCLOCKNETS</td> +</tr> +<tr> +<td>-read_cores</td> +<td>Read Cores</td> +<td>YES</td> +<td>YES</td> +</tr> +<tr> +<td>-write_timing_constraints</td> +<td>Write Timing Constraints</td> +<td>NO</td> +<td>NO</td> +</tr> +<tr> +<td>-cross_clock_analysis</td> +<td>Cross Clock Analysis</td> +<td>NO</td> +<td>NO</td> +</tr> +<tr> +<td>-bus_delimiter</td> +<td>Bus Delimiter</td> +<td><></td> +<td><></td> +</tr> +<tr> +<td>-slice_utilization_ratio</td> +<td>Slice Utilization Ratio</td> +<td>100</td> +<td>100%</td> +</tr> +<tr> +<td>-bram_utilization_ratio</td> +<td>BRAM Utilization Ratio</td> +<td>100</td> +<td>100%</td> +</tr> +<tr> +<td>-verilog2001</td> +<td>Verilog 2001</td> +<td>YES</td> +<td>YES</td> +</tr> +<tr> +<td>-fsm_extract</td> +<td> </td> +<td>YES</td> +<td>YES</td> +</tr> +<tr> +<td>-fsm_encoding</td> +<td> </td> +<td>Auto</td> +<td>AUTO</td> +</tr> +<tr> +<td>-safe_implementation</td> +<td> </td> +<td>No</td> +<td>NO</td> +</tr> +<tr> +<td>-fsm_style</td> +<td> </td> +<td>LUT</td> +<td>LUT</td> +</tr> +<tr> +<td>-ram_extract</td> +<td> </td> +<td>Yes</td> +<td>YES</td> +</tr> +<tr> +<td>-ram_style</td> +<td> </td> +<td>Auto</td> +<td>AUTO</td> +</tr> +<tr> +<td>-rom_extract</td> +<td> </td> +<td>Yes</td> +<td>YES</td> +</tr> +<tr> +<td>-shreg_extract</td> +<td> </td> +<td>YES</td> +<td>YES</td> +</tr> +<tr> +<td>-rom_style</td> +<td> </td> +<td>Auto</td> +<td>AUTO</td> +</tr> +<tr> +<td>-auto_bram_packing</td> +<td> </td> +<td>NO</td> +<td>NO</td> +</tr> +<tr> +<td>-resource_sharing</td> +<td> </td> +<td>YES</td> +<td>YES</td> +</tr> +<tr> +<td>-async_to_sync</td> +<td> </td> +<td>NO</td> +<td>NO</td> +</tr> +<tr> +<td>-mult_style</td> +<td> </td> +<td>Auto</td> +<td>AUTO</td> +</tr> +<tr> +<td>-iobuf</td> +<td> </td> +<td>YES</td> +<td>YES</td> +</tr> +<tr> +<td>-max_fanout</td> +<td> </td> +<td>500</td> +<td>500</td> +</tr> +<tr> +<td>-bufg</td> +<td> </td> +<td>24</td> +<td>24</td> +</tr> +<tr> +<td>-register_duplication</td> +<td> </td> +<td>YES</td> +<td>YES</td> +</tr> +<tr> +<td>-register_balancing</td> +<td> </td> +<td>No</td> +<td>NO</td> +</tr> +<tr> +<td>-optimize_primitives</td> +<td> </td> +<td>NO</td> +<td>NO</td> +</tr> +<tr> +<td>-use_clock_enable</td> +<td> </td> +<td>Yes</td> +<td>YES</td> +</tr> +<tr> +<td>-use_sync_set</td> +<td> </td> +<td>Yes</td> +<td>YES</td> +</tr> +<tr> +<td>-use_sync_reset</td> +<td> </td> +<td>Yes</td> +<td>YES</td> +</tr> +<tr> +<td>-iob</td> +<td> </td> +<td>Auto</td> +<td>AUTO</td> +</tr> +<tr> +<td>-equivalent_register_removal</td> +<td> </td> +<td>YES</td> +<td>YES</td> +</tr> +<tr> +<td>-slice_utilization_ratio_maxmargin</td> +<td> </td> +<td>5</td> +<td>0%</td> +</tr> +</TABLE> +<A NAME="Operating System Information"></A> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD> +</tr> +<tr bgcolor='#ffff99'> +<td><b>Operating System Information</b></td> +<td><b>xst</b></td> +<td><b>ngdbuild</b></td> +<td><b>map</b></td> +<td><b>par</b></td> +</tr> +<tr> +<td>CPU Architecture/Speed</td> +<td>Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz/3099.957 MHz</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>Host</td> +<td>yann-arch</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>OS Name</td> +<td>unknown</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>OS Release</td> +<td>unknown</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +</TABLE> +</BODY> </HTML>
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