Working blinking lightHEADmaster

13 files changed, 1636 insertions, 0 deletions

diff --git a/planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif b/planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif
new file mode 100644
index 0000000..d478d16
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif
@@ -0,0 +1,1286 @@
+(edif led
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2017 2 21 21 50 3)
+      (program "Xilinx ngc2edif" (version "P.20131013"))
+      (author "Xilinx. Inc ")
+      (comment "This EDIF netlist is to be used within supported synthesis tools")
+      (comment "for determining resource/timing estimates of the design component")
+      (comment "represented by this netlist.")
+      (comment "Command line: -mdp2sp -w -secure led.ngc led.edif ")))
+  (external UNISIMS
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell VCC
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port P
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell GND
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port G
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell MUXCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port DI
+              (direction INPUT)
+            )
+            (port S
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell XORCY
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CI
+              (direction INPUT)
+            )
+            (port LI
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT6
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port I3
+              (direction INPUT)
+            )
+            (port I4
+              (direction INPUT)
+            )
+            (port I5
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell OBUF
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT1
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT3
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port I2
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell FD
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port C
+              (direction INPUT)
+            )
+            (port D
+              (direction INPUT)
+            )
+            (port Q
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell LUT2
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I0
+              (direction INPUT)
+            )
+            (port I1
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell BUFGP
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+    (cell INV
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port I
+              (direction INPUT)
+            )
+            (port O
+              (direction OUTPUT)
+            )
+          )
+      )
+    )
+  )
+
+  (library led_lib
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell led
+      (cellType GENERIC)
+        (view view_1
+          (viewType NETLIST)
+          (interface
+            (port CLK
+              (direction INPUT)
+            )
+            (port LED1
+              (direction OUTPUT)
+            )
+            (designator "xc6slx9-2-tqg144")
+            (property TYPE (string "led") (owner "Xilinx"))
+            (property SHREG_MIN_SIZE (string "2") (owner "Xilinx"))
+            (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx"))
+            (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+            (property NLW_MACRO_ALIAS (string "led_led") (owner "Xilinx"))
+          )
+          (contents
+            (instance XST_VCC
+              (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance XST_GND
+              (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_0___renamed_0 "Mcount_count_cy<0>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_0__ "Mcount_count_xor<0>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_1___renamed_1 "Mcount_count_cy<1>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_1__ "Mcount_count_xor<1>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_2___renamed_2 "Mcount_count_cy<2>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_2__ "Mcount_count_xor<2>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_3___renamed_3 "Mcount_count_cy<3>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_3__ "Mcount_count_xor<3>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_4___renamed_4 "Mcount_count_cy<4>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_4__ "Mcount_count_xor<4>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_5___renamed_5 "Mcount_count_cy<5>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_5__ "Mcount_count_xor<5>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_6___renamed_6 "Mcount_count_cy<6>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_6__ "Mcount_count_xor<6>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_7___renamed_7 "Mcount_count_cy<7>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_7__ "Mcount_count_xor<7>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_8___renamed_8 "Mcount_count_cy<8>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_8__ "Mcount_count_xor<8>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_9___renamed_9 "Mcount_count_cy<9>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_9__ "Mcount_count_xor<9>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_10___renamed_10 "Mcount_count_cy<10>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_10__ "Mcount_count_xor<10>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_11___renamed_11 "Mcount_count_cy<11>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_11__ "Mcount_count_xor<11>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_12___renamed_12 "Mcount_count_cy<12>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_12__ "Mcount_count_xor<12>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_13___renamed_13 "Mcount_count_cy<13>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_13__ "Mcount_count_xor<13>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_14___renamed_14 "Mcount_count_cy<14>")
+              (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_14__ "Mcount_count_xor<14>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_xor_15__ "Mcount_count_xor<15>")
+              (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename count_15__GND_1_o_equal_2_o_15_1_renamed_15 "count[15]_GND_1_o_equal_2_o<15>1")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename count_15__GND_1_o_equal_2_o_15_2 "count[15]_GND_1_o_equal_2_o<15>2")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0000000000000001") (owner "Xilinx"))
+            )
+            (instance (rename count_15__GND_1_o_equal_2_o_15_3 "count[15]_GND_1_o_equal_2_o<15>3")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0001000000000000") (owner "Xilinx"))
+            )
+            (instance (rename LED1_OBUF_renamed_16 "LED1_OBUF")
+              (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_cy_0__rt_renamed_17 "Mcount_count_cy<0>_rt")
+              (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance (rename LED1_dpot_renamed_18 "LED1_dpot")
+              (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "AAAAAAA9AAAAAAAA") (owner "Xilinx"))
+            )
+            (instance (rename LED1_rstpot_renamed_19 "LED1_rstpot")
+              (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E2") (owner "Xilinx"))
+            )
+            (instance (rename LED1_renamed_20 "LED1")
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_1_rstpot_renamed_21 "count_1_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_1
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_0_rstpot_renamed_22 "count_0_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_0
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_2_rstpot_renamed_23 "count_2_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_2
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_3_rstpot_renamed_24 "count_3_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_3
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_4_rstpot_renamed_25 "count_4_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_4
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_5_rstpot_renamed_26 "count_5_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_5
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_6_rstpot_renamed_27 "count_6_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_6
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_7_rstpot_renamed_28 "count_7_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_7
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_8_rstpot_renamed_29 "count_8_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_8
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_9_rstpot_renamed_30 "count_9_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_9
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_10_rstpot_renamed_31 "count_10_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_10
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_11_rstpot_renamed_32 "count_11_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_11
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_12_rstpot_renamed_33 "count_12_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_12
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_13_rstpot_renamed_34 "count_13_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "2") (owner "Xilinx"))
+            )
+            (instance count_13
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "0") (owner "Xilinx"))
+            )
+            (instance (rename count_14_rstpot_renamed_35 "count_14_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_14
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename count_15_rstpot_renamed_36 "count_15_rstpot")
+              (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "E") (owner "Xilinx"))
+            )
+            (instance count_15
+              (viewRef view_1 (cellRef FD (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+              (property INIT (string "1") (owner "Xilinx"))
+            )
+            (instance (rename CLK_BUFGP_renamed_37 "CLK_BUFGP")
+              (viewRef view_1 (cellRef BUFGP (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_1__INV_0 "Mcount_count_lut<1>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_2__INV_0 "Mcount_count_lut<2>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_3__INV_0 "Mcount_count_lut<3>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_4__INV_0 "Mcount_count_lut<4>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_5__INV_0 "Mcount_count_lut<5>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_6__INV_0 "Mcount_count_lut<6>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_7__INV_0 "Mcount_count_lut<7>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_8__INV_0 "Mcount_count_lut<8>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_9__INV_0 "Mcount_count_lut<9>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_10__INV_0 "Mcount_count_lut<10>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_11__INV_0 "Mcount_count_lut<11>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_12__INV_0 "Mcount_count_lut<12>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_13__INV_0 "Mcount_count_lut<13>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_14__INV_0 "Mcount_count_lut<14>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (instance (rename Mcount_count_lut_15__INV_0 "Mcount_count_lut<15>_INV_0")
+              (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+              (property XSTLIB (boolean (true)) (owner "Xilinx"))
+            )
+            (net CLK_BUFGP
+              (joined
+                (portRef C (instanceRef LED1_renamed_20))
+                (portRef C (instanceRef count_1))
+                (portRef C (instanceRef count_0))
+                (portRef C (instanceRef count_2))
+                (portRef C (instanceRef count_3))
+                (portRef C (instanceRef count_4))
+                (portRef C (instanceRef count_5))
+                (portRef C (instanceRef count_6))
+                (portRef C (instanceRef count_7))
+                (portRef C (instanceRef count_8))
+                (portRef C (instanceRef count_9))
+                (portRef C (instanceRef count_10))
+                (portRef C (instanceRef count_11))
+                (portRef C (instanceRef count_12))
+                (portRef C (instanceRef count_13))
+                (portRef C (instanceRef count_14))
+                (portRef C (instanceRef count_15))
+                (portRef O (instanceRef CLK_BUFGP_renamed_37))
+              )
+            )
+            (net (rename count_15__ "count<15>")
+              (joined
+                (portRef I4 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_15))
+                (portRef I (instanceRef Mcount_count_lut_15__INV_0))
+                (portRef I0 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_14__ "count<14>")
+              (joined
+                (portRef I3 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_14))
+                (portRef I (instanceRef Mcount_count_lut_14__INV_0))
+                (portRef I1 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_13__ "count<13>")
+              (joined
+                (portRef I1 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_13))
+                (portRef I (instanceRef Mcount_count_lut_13__INV_0))
+                (portRef I3 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_12__ "count<12>")
+              (joined
+                (portRef I2 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef count_12))
+                (portRef I (instanceRef Mcount_count_lut_12__INV_0))
+                (portRef I2 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_11__ "count<11>")
+              (joined
+                (portRef I5 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_11))
+                (portRef I (instanceRef Mcount_count_lut_11__INV_0))
+              )
+            )
+            (net (rename count_10__ "count<10>")
+              (joined
+                (portRef I4 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_10))
+                (portRef I (instanceRef Mcount_count_lut_10__INV_0))
+              )
+            )
+            (net (rename count_9__ "count<9>")
+              (joined
+                (portRef I3 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_9))
+                (portRef I (instanceRef Mcount_count_lut_9__INV_0))
+              )
+            )
+            (net (rename count_8__ "count<8>")
+              (joined
+                (portRef I2 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_8))
+                (portRef I (instanceRef Mcount_count_lut_8__INV_0))
+              )
+            )
+            (net (rename count_7__ "count<7>")
+              (joined
+                (portRef I0 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_7))
+                (portRef I (instanceRef Mcount_count_lut_7__INV_0))
+              )
+            )
+            (net (rename count_6__ "count<6>")
+              (joined
+                (portRef I1 (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef Q (instanceRef count_6))
+                (portRef I (instanceRef Mcount_count_lut_6__INV_0))
+              )
+            )
+            (net (rename count_5__ "count<5>")
+              (joined
+                (portRef I5 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_5))
+                (portRef I (instanceRef Mcount_count_lut_5__INV_0))
+              )
+            )
+            (net (rename count_4__ "count<4>")
+              (joined
+                (portRef I4 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_4))
+                (portRef I (instanceRef Mcount_count_lut_4__INV_0))
+              )
+            )
+            (net (rename count_3__ "count<3>")
+              (joined
+                (portRef I3 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_3))
+                (portRef I (instanceRef Mcount_count_lut_3__INV_0))
+              )
+            )
+            (net (rename count_2__ "count<2>")
+              (joined
+                (portRef I2 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_2))
+                (portRef I (instanceRef Mcount_count_lut_2__INV_0))
+              )
+            )
+            (net (rename count_1__ "count<1>")
+              (joined
+                (portRef I0 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef Q (instanceRef count_1))
+                (portRef I (instanceRef Mcount_count_lut_1__INV_0))
+              )
+            )
+            (net (rename count_0__ "count<0>")
+              (joined
+                (portRef I1 (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef I0 (instanceRef Mcount_count_cy_0__rt_renamed_17))
+                (portRef Q (instanceRef count_0))
+              )
+            )
+            (net LED1_OBUF
+              (joined
+                (portRef I (instanceRef LED1_OBUF_renamed_16))
+                (portRef I0 (instanceRef LED1_dpot_renamed_18))
+                (portRef Q (instanceRef LED1_renamed_20))
+                (portRef I0 (instanceRef LED1_rstpot_renamed_19))
+              )
+            )
+            (net (rename count_15__GND_1_o_equal_2_o "count[15]_GND_1_o_equal_2_o")
+              (joined
+                (portRef O (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+                (portRef I1 (instanceRef count_1_rstpot_renamed_21))
+                (portRef I1 (instanceRef count_0_rstpot_renamed_22))
+                (portRef I1 (instanceRef count_2_rstpot_renamed_23))
+                (portRef I1 (instanceRef count_3_rstpot_renamed_24))
+                (portRef I1 (instanceRef count_4_rstpot_renamed_25))
+                (portRef I1 (instanceRef count_5_rstpot_renamed_26))
+                (portRef I1 (instanceRef count_6_rstpot_renamed_27))
+                (portRef I1 (instanceRef count_7_rstpot_renamed_28))
+                (portRef I1 (instanceRef count_8_rstpot_renamed_29))
+                (portRef I1 (instanceRef count_9_rstpot_renamed_30))
+                (portRef I1 (instanceRef count_10_rstpot_renamed_31))
+                (portRef I1 (instanceRef count_11_rstpot_renamed_32))
+                (portRef I1 (instanceRef count_12_rstpot_renamed_33))
+                (portRef I1 (instanceRef count_13_rstpot_renamed_34))
+                (portRef I1 (instanceRef count_14_rstpot_renamed_35))
+                (portRef I1 (instanceRef count_15_rstpot_renamed_36))
+              )
+            )
+            (net N0
+              (joined
+                (portRef P (instanceRef XST_VCC))
+                (portRef CI (instanceRef Mcount_count_cy_0___renamed_0))
+                (portRef CI (instanceRef Mcount_count_xor_0__))
+                (portRef DI (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef DI (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef DI (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef DI (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef DI (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef DI (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef DI (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef DI (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef DI (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef DI (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef DI (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef DI (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef DI (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef DI (instanceRef Mcount_count_cy_14___renamed_14))
+              )
+            )
+            (net N1
+              (joined
+                (portRef G (instanceRef XST_GND))
+                (portRef DI (instanceRef Mcount_count_cy_0___renamed_0))
+              )
+            )
+            (net (rename Result_0__ "Result<0>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_0__))
+                (portRef I0 (instanceRef count_0_rstpot_renamed_22))
+              )
+            )
+            (net (rename Result_1__ "Result<1>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_1__))
+                (portRef I0 (instanceRef count_1_rstpot_renamed_21))
+              )
+            )
+            (net (rename Result_2__ "Result<2>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_2__))
+                (portRef I0 (instanceRef count_2_rstpot_renamed_23))
+              )
+            )
+            (net (rename Result_3__ "Result<3>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_3__))
+                (portRef I0 (instanceRef count_3_rstpot_renamed_24))
+              )
+            )
+            (net (rename Result_4__ "Result<4>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_4__))
+                (portRef I0 (instanceRef count_4_rstpot_renamed_25))
+              )
+            )
+            (net (rename Result_5__ "Result<5>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_5__))
+                (portRef I0 (instanceRef count_5_rstpot_renamed_26))
+              )
+            )
+            (net (rename Result_6__ "Result<6>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_6__))
+                (portRef I0 (instanceRef count_6_rstpot_renamed_27))
+              )
+            )
+            (net (rename Result_7__ "Result<7>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_7__))
+                (portRef I0 (instanceRef count_7_rstpot_renamed_28))
+              )
+            )
+            (net (rename Result_8__ "Result<8>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_8__))
+                (portRef I0 (instanceRef count_8_rstpot_renamed_29))
+              )
+            )
+            (net (rename Result_9__ "Result<9>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_9__))
+                (portRef I0 (instanceRef count_9_rstpot_renamed_30))
+              )
+            )
+            (net (rename Result_10__ "Result<10>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_10__))
+                (portRef I0 (instanceRef count_10_rstpot_renamed_31))
+              )
+            )
+            (net (rename Result_11__ "Result<11>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_11__))
+                (portRef I0 (instanceRef count_11_rstpot_renamed_32))
+              )
+            )
+            (net (rename Result_12__ "Result<12>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_12__))
+                (portRef I0 (instanceRef count_12_rstpot_renamed_33))
+              )
+            )
+            (net (rename Result_13__ "Result<13>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_13__))
+                (portRef I0 (instanceRef count_13_rstpot_renamed_34))
+              )
+            )
+            (net (rename Result_14__ "Result<14>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_14__))
+                (portRef I0 (instanceRef count_14_rstpot_renamed_35))
+              )
+            )
+            (net (rename Result_15__ "Result<15>")
+              (joined
+                (portRef O (instanceRef Mcount_count_xor_15__))
+                (portRef I0 (instanceRef count_15_rstpot_renamed_36))
+              )
+            )
+            (net (rename Mcount_count_cy_0__ "Mcount_count_cy<0>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_0___renamed_0))
+                (portRef CI (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef CI (instanceRef Mcount_count_xor_1__))
+              )
+            )
+            (net (rename Mcount_count_lut_1__ "Mcount_count_lut<1>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef LI (instanceRef Mcount_count_xor_1__))
+                (portRef O (instanceRef Mcount_count_lut_1__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_1__ "Mcount_count_cy<1>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_1___renamed_1))
+                (portRef CI (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef CI (instanceRef Mcount_count_xor_2__))
+              )
+            )
+            (net (rename Mcount_count_lut_2__ "Mcount_count_lut<2>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef LI (instanceRef Mcount_count_xor_2__))
+                (portRef O (instanceRef Mcount_count_lut_2__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_2__ "Mcount_count_cy<2>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_2___renamed_2))
+                (portRef CI (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef CI (instanceRef Mcount_count_xor_3__))
+              )
+            )
+            (net (rename Mcount_count_lut_3__ "Mcount_count_lut<3>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef LI (instanceRef Mcount_count_xor_3__))
+                (portRef O (instanceRef Mcount_count_lut_3__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_3__ "Mcount_count_cy<3>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_3___renamed_3))
+                (portRef CI (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef CI (instanceRef Mcount_count_xor_4__))
+              )
+            )
+            (net (rename Mcount_count_lut_4__ "Mcount_count_lut<4>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef LI (instanceRef Mcount_count_xor_4__))
+                (portRef O (instanceRef Mcount_count_lut_4__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_4__ "Mcount_count_cy<4>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_4___renamed_4))
+                (portRef CI (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef CI (instanceRef Mcount_count_xor_5__))
+              )
+            )
+            (net (rename Mcount_count_lut_5__ "Mcount_count_lut<5>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef LI (instanceRef Mcount_count_xor_5__))
+                (portRef O (instanceRef Mcount_count_lut_5__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_5__ "Mcount_count_cy<5>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_5___renamed_5))
+                (portRef CI (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef CI (instanceRef Mcount_count_xor_6__))
+              )
+            )
+            (net (rename Mcount_count_lut_6__ "Mcount_count_lut<6>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef LI (instanceRef Mcount_count_xor_6__))
+                (portRef O (instanceRef Mcount_count_lut_6__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_6__ "Mcount_count_cy<6>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_6___renamed_6))
+                (portRef CI (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef CI (instanceRef Mcount_count_xor_7__))
+              )
+            )
+            (net (rename Mcount_count_lut_7__ "Mcount_count_lut<7>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef LI (instanceRef Mcount_count_xor_7__))
+                (portRef O (instanceRef Mcount_count_lut_7__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_7__ "Mcount_count_cy<7>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_7___renamed_7))
+                (portRef CI (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef CI (instanceRef Mcount_count_xor_8__))
+              )
+            )
+            (net (rename Mcount_count_lut_8__ "Mcount_count_lut<8>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef LI (instanceRef Mcount_count_xor_8__))
+                (portRef O (instanceRef Mcount_count_lut_8__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_8__ "Mcount_count_cy<8>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_8___renamed_8))
+                (portRef CI (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef CI (instanceRef Mcount_count_xor_9__))
+              )
+            )
+            (net (rename Mcount_count_lut_9__ "Mcount_count_lut<9>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef LI (instanceRef Mcount_count_xor_9__))
+                (portRef O (instanceRef Mcount_count_lut_9__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_9__ "Mcount_count_cy<9>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_9___renamed_9))
+                (portRef CI (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef CI (instanceRef Mcount_count_xor_10__))
+              )
+            )
+            (net (rename Mcount_count_lut_10__ "Mcount_count_lut<10>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef LI (instanceRef Mcount_count_xor_10__))
+                (portRef O (instanceRef Mcount_count_lut_10__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_10__ "Mcount_count_cy<10>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_10___renamed_10))
+                (portRef CI (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef CI (instanceRef Mcount_count_xor_11__))
+              )
+            )
+            (net (rename Mcount_count_lut_11__ "Mcount_count_lut<11>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef LI (instanceRef Mcount_count_xor_11__))
+                (portRef O (instanceRef Mcount_count_lut_11__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_11__ "Mcount_count_cy<11>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_11___renamed_11))
+                (portRef CI (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef CI (instanceRef Mcount_count_xor_12__))
+              )
+            )
+            (net (rename Mcount_count_lut_12__ "Mcount_count_lut<12>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef LI (instanceRef Mcount_count_xor_12__))
+                (portRef O (instanceRef Mcount_count_lut_12__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_12__ "Mcount_count_cy<12>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_12___renamed_12))
+                (portRef CI (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef CI (instanceRef Mcount_count_xor_13__))
+              )
+            )
+            (net (rename Mcount_count_lut_13__ "Mcount_count_lut<13>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef LI (instanceRef Mcount_count_xor_13__))
+                (portRef O (instanceRef Mcount_count_lut_13__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_13__ "Mcount_count_cy<13>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_13___renamed_13))
+                (portRef CI (instanceRef Mcount_count_cy_14___renamed_14))
+                (portRef CI (instanceRef Mcount_count_xor_14__))
+              )
+            )
+            (net (rename Mcount_count_lut_14__ "Mcount_count_lut<14>")
+              (joined
+                (portRef S (instanceRef Mcount_count_cy_14___renamed_14))
+                (portRef LI (instanceRef Mcount_count_xor_14__))
+                (portRef O (instanceRef Mcount_count_lut_14__INV_0))
+              )
+            )
+            (net (rename Mcount_count_cy_14__ "Mcount_count_cy<14>")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_14___renamed_14))
+                (portRef CI (instanceRef Mcount_count_xor_15__))
+              )
+            )
+            (net (rename Mcount_count_lut_15__ "Mcount_count_lut<15>")
+              (joined
+                (portRef LI (instanceRef Mcount_count_xor_15__))
+                (portRef O (instanceRef Mcount_count_lut_15__INV_0))
+              )
+            )
+            (net (rename count_15__GND_1_o_equal_2_o_15__ "count[15]_GND_1_o_equal_2_o<15>")
+              (joined
+                (portRef O (instanceRef count_15__GND_1_o_equal_2_o_15_1_renamed_15))
+                (portRef I5 (instanceRef LED1_dpot_renamed_18))
+                (portRef I4 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+              )
+            )
+            (net (rename count_15__GND_1_o_equal_2_o_15_1 "count[15]_GND_1_o_equal_2_o<15>1")
+              (joined
+                (portRef O (instanceRef count_15__GND_1_o_equal_2_o_15_2))
+                (portRef I5 (instanceRef count_15__GND_1_o_equal_2_o_15_3))
+                (portRef I1 (instanceRef LED1_rstpot_renamed_19))
+              )
+            )
+            (net CLK
+              (joined
+                (portRef CLK)
+                (portRef I (instanceRef CLK_BUFGP_renamed_37))
+              )
+            )
+            (net LED1
+              (joined
+                (portRef LED1)
+                (portRef O (instanceRef LED1_OBUF_renamed_16))
+              )
+            )
+            (net (rename Mcount_count_cy_0__rt "Mcount_count_cy<0>_rt")
+              (joined
+                (portRef O (instanceRef Mcount_count_cy_0__rt_renamed_17))
+                (portRef S (instanceRef Mcount_count_cy_0___renamed_0))
+                (portRef LI (instanceRef Mcount_count_xor_0__))
+              )
+            )
+            (net LED1_dpot
+              (joined
+                (portRef O (instanceRef LED1_dpot_renamed_18))
+                (portRef I2 (instanceRef LED1_rstpot_renamed_19))
+              )
+            )
+            (net LED1_rstpot
+              (joined
+                (portRef O (instanceRef LED1_rstpot_renamed_19))
+                (portRef D (instanceRef LED1_renamed_20))
+              )
+            )
+            (net count_1_rstpot
+              (joined
+                (portRef O (instanceRef count_1_rstpot_renamed_21))
+                (portRef D (instanceRef count_1))
+              )
+            )
+            (net count_0_rstpot
+              (joined
+                (portRef O (instanceRef count_0_rstpot_renamed_22))
+                (portRef D (instanceRef count_0))
+              )
+            )
+            (net count_2_rstpot
+              (joined
+                (portRef O (instanceRef count_2_rstpot_renamed_23))
+                (portRef D (instanceRef count_2))
+              )
+            )
+            (net count_3_rstpot
+              (joined
+                (portRef O (instanceRef count_3_rstpot_renamed_24))
+                (portRef D (instanceRef count_3))
+              )
+            )
+            (net count_4_rstpot
+              (joined
+                (portRef O (instanceRef count_4_rstpot_renamed_25))
+                (portRef D (instanceRef count_4))
+              )
+            )
+            (net count_5_rstpot
+              (joined
+                (portRef O (instanceRef count_5_rstpot_renamed_26))
+                (portRef D (instanceRef count_5))
+              )
+            )
+            (net count_6_rstpot
+              (joined
+                (portRef O (instanceRef count_6_rstpot_renamed_27))
+                (portRef D (instanceRef count_6))
+              )
+            )
+            (net count_7_rstpot
+              (joined
+                (portRef O (instanceRef count_7_rstpot_renamed_28))
+                (portRef D (instanceRef count_7))
+              )
+            )
+            (net count_8_rstpot
+              (joined
+                (portRef O (instanceRef count_8_rstpot_renamed_29))
+                (portRef D (instanceRef count_8))
+              )
+            )
+            (net count_9_rstpot
+              (joined
+                (portRef O (instanceRef count_9_rstpot_renamed_30))
+                (portRef D (instanceRef count_9))
+              )
+            )
+            (net count_10_rstpot
+              (joined
+                (portRef O (instanceRef count_10_rstpot_renamed_31))
+                (portRef D (instanceRef count_10))
+              )
+            )
+            (net count_11_rstpot
+              (joined
+                (portRef O (instanceRef count_11_rstpot_renamed_32))
+                (portRef D (instanceRef count_11))
+              )
+            )
+            (net count_12_rstpot
+              (joined
+                (portRef O (instanceRef count_12_rstpot_renamed_33))
+                (portRef D (instanceRef count_12))
+              )
+            )
+            (net count_13_rstpot
+              (joined
+                (portRef O (instanceRef count_13_rstpot_renamed_34))
+                (portRef D (instanceRef count_13))
+              )
+            )
+            (net count_14_rstpot
+              (joined
+                (portRef O (instanceRef count_14_rstpot_renamed_35))
+                (portRef D (instanceRef count_14))
+              )
+            )
+            (net count_15_rstpot
+              (joined
+                (portRef O (instanceRef count_15_rstpot_renamed_36))
+                (portRef D (instanceRef count_15))
+              )
+            )
+          )
+      )
+    )
+  )
+
+  (design led
+    (cellRef led
+      (libraryRef led_lib)
+    )
+    (property PART (string "xc6slx9-2-tqg144") (owner "Xilinx"))
+  )
+)
+
diff --git a/planAhead_run_4/FPGA-led-lights.data/constrs_1/fileset.xml b/planAhead_run_4/FPGA-led-lights.data/constrs_1/fileset.xml
new file mode 100644
index 0000000..27cbdc8
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/constrs_1/fileset.xml
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../../../Downloads/BPC3011-Papilio_Pro-general.ucf">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="TargetConstrsFile" Val="$PPRDIR/../../../Downloads/BPC3011-Papilio_Pro-general.ucf"/>
+      <Option Name="ConstrsType" Val="UCF"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_4/FPGA-led-lights.data/runs/impl_1.psg b/planAhead_run_4/FPGA-led-lights.data/runs/impl_1.psg
new file mode 100644
index 0000000..147f3a9
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/runs/impl_1.psg
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+	<StratHandle Name="ISE Defaults" Flow="ISE14">
+		<Desc>ISE Defaults, including packing registers in IOs off</Desc>
+	</StratHandle>
+	<Step Id="ngdbuild">
+	</Step>
+	<Step Id="map">
+		<Option Id="FFPackEnum">3</Option>
+	</Step>
+	<Step Id="par">
+	</Step>
+	<Step Id="trce">
+	</Step>
+	<Step Id="xdl">
+	</Step>
+	<Step Id="bitgen">
+	</Step>
+</Strategy>
+
diff --git a/planAhead_run_4/FPGA-led-lights.data/runs/runs.xml b/planAhead_run_4/FPGA-led-lights.data/runs/runs.xml
new file mode 100644
index 0000000..7708ac8
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/runs/runs.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+	<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx9tqg144-2" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/>
+</Runs>
+
diff --git a/planAhead_run_4/FPGA-led-lights.data/sim_1/fileset.xml b/planAhead_run_4/FPGA-led-lights.data/sim_1/fileset.xml
new file mode 100644
index 0000000..65babe3
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/sim_1/fileset.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+      <Option Name="SrcSet" Val="sources_1"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_4/FPGA-led-lights.data/sources_1/fileset.xml b/planAhead_run_4/FPGA-led-lights.data/sources_1/fileset.xml
new file mode 100644
index 0000000..ddc517f
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/sources_1/fileset.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1" Minor="26">
+  <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+    <Filter Type="EDIFSrcs"/>
+    <File Path="$PPRDIR/../led.ngc">
+      <FileInfo>
+        <Attr Name="UsedInSynthesis" Val="1"/>
+        <Attr Name="UsedInImplementation" Val="1"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="GateLvl"/>
+      <Option Name="GateLvlMode" Val="EDIF"/>
+      <Option Name="TopFile" Val="$PPRDIR/../led.ngc"/>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+</DARoots>
diff --git a/planAhead_run_4/FPGA-led-lights.data/wt/java_command_handlers.wdf b/planAhead_run_4/FPGA-led-lights.data/wt/java_command_handlers.wdf
new file mode 100644
index 0000000..90b0b33
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/wt/java_command_handlers.wdf
@@ -0,0 +1,4 @@
+version:1
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e736372697074:31:00:00
+70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:32:00:00
+eof:2778578561
diff --git a/planAhead_run_4/FPGA-led-lights.data/wt/project.wpc b/planAhead_run_4/FPGA-led-lights.data/wt/project.wpc
new file mode 100644
index 0000000..5fed558
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/wt/project.wpc
@@ -0,0 +1,4 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4953454d6f6465:1
+eof:
diff --git a/planAhead_run_4/FPGA-led-lights.data/wt/webtalk_pa.xml b/planAhead_run_4/FPGA-led-lights.data/wt/webtalk_pa.xml
new file mode 100644
index 0000000..0ab2f73
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.data/wt/webtalk_pa.xml
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Tue Feb 21 21:53:14 2017">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="5839cde962314e60853ae32f9ffcb4a0" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="GateLvl" type="DesignMode"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="RunScript" value="1" type="JavaHandler"/>
+<property name="ShowView" value="2" type="JavaHandler"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="0" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="7" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/planAhead_run_4/FPGA-led-lights.ppr b/planAhead_run_4/FPGA-led-lights.ppr
new file mode 100644
index 0000000..42d291d
--- /dev/null
+++ b/planAhead_run_4/FPGA-led-lights.ppr
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!--Product Version: PlanAhead v14.7 (64-bit)-->
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<RunSet Dir="runs" File="runs.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="903fcee33e314607aca91ab5aed60bb7"/>
+		<Option Name="Part" Val="xc6slx9tqg144-2"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+		<Option Name="TargetLanguage" Val="Verilog"/>
+		<Option Name="TargetSimulator" Val="ISim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="All"/>
+		<Option Name="ActiveSimSet" Val="sim_1"/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
diff --git a/planAhead_run_4/planAhead.jou b/planAhead_run_4/planAhead.jou
new file mode 100644
index 0000000..236855b
--- /dev/null
+++ b/planAhead_run_4/planAhead.jou
@@ -0,0 +1,14 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Start of session at: Tue Feb 21 21:49:52 2017
+# Process ID: 24218
+# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4/planAhead.log
+# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4/planAhead.jou
+#-----------------------------------------------------------
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNcd.tcl
+add wave clock enable
+create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
+add
+run
diff --git a/planAhead_run_4/planAhead.log b/planAhead_run_4/planAhead.log
new file mode 100644
index 0000000..00270f3
--- /dev/null
+++ b/planAhead_run_4/planAhead.log
@@ -0,0 +1,96 @@
+#-----------------------------------------------------------
+# PlanAhead v14.7 (64-bit)
+# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+# Start of session at: Tue Feb 21 21:49:52 2017
+# Process ID: 24218
+# Log file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4/planAhead.log
+# Journal file: /home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4/planAhead.jou
+#-----------------------------------------------------------
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNcd.tcl
+# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4" -part xc6slx9tqg144-2
+# set srcset [get_property srcset [current_run -impl]]
+# set_property design_mode GateLvl $srcset
+# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} }
+# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1'
+# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc6slx9tqg144-2
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design led.ngc ...
+WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file led.edif ...
+ngc2edif: Total memory usage is 103540 kilobytes
+
+Parsing EDIF File [./planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+Finished Parsing EDIF File [./planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 1 instances were transformed.
+  BUFGP => BUFGP (IBUF, BUFG): 1 instances
+
+Phase 0 | Netlist Checksum: 23693229
+link_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2864.305 ; gain = 189.508
+# read_xdl -file "/home/yannherklotz/Github/FPGA-led-lights/led.ncd"
+Release 14.7 - xdl P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
+Loading device for application Rf_Device from file '6slx9.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
+   "led" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
+Successfully converted design '/home/yannherklotz/Github/FPGA-led-lights/led.ncd' to '/home/yannherklotz/Github/FPGA-led-lights/led.xdl'.
+INFO: [Designutils 20-669] Parsing Placement File : /home/yannherklotz/Github/FPGA-led-lights/led.ncd
+INFO: [Designutils 20-658] Finished Parsing Placement File : /home/yannherklotz/Github/FPGA-led-lights/led.ncd
+INFO: [Designutils 20-671] Placed 87 instances
+read_xdl: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 2864.305 ; gain = 0.000
+# if {[catch {read_twx -name results_1 -file "/home/yannherklotz/Github/FPGA-led-lights/led.twx"} eInfo]} {
+#    puts "WARNING: there was a problem importing \"/home/yannherklotz/Github/FPGA-led-lights/led.twx\": $eInfo"
+# }
+add wave clock enable
+invalid command name "add"
+ambiguous command name "add": add_cells_to_pblock add_files
+create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
+WARNING: [PlanAhead 12-584] No ports matched 'CLOCK_50'.
+invalid command name "create_clock"
+add
+invalid command name "add"
+ambiguous command name "add": add_cells_to_pblock add_files
+run
+invalid command name "run"
+exit
+ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
+HTclEvent: DEBUG_PORT_CONFIG_CHANGE   Classes: ui.views.aR 
+HTclEvent: SIGNAL_BUS_MODIFY   Classes: ui.views.aR 
+HTclEvent: SIGNAL_MODIFY   Classes: ui.views.aR 
+HTclEvent: DEBUG_CORE_CONFIG_CHANGE   Classes: ui.views.aR 
+ (See /home/yannherklotz/Github/FPGA-led-lights/planAhead_pid24218.debug)
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 21:53:15 2017...
+INFO: [Common 17-83] Releasing license: PlanAhead
diff --git a/planAhead_run_4/planAhead_run.log b/planAhead_run_4/planAhead_run.log
new file mode 100644
index 0000000..39a91d8
--- /dev/null
+++ b/planAhead_run_4/planAhead_run.log
@@ -0,0 +1,105 @@
+
+****** PlanAhead v14.7 (64-bit)
+  **** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
+    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+
+INFO: [Common 17-78] Attempting to get a license: PlanAhead
+INFO: [Common 17-290] Got license for PlanAhead
+INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
+Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
+start_gui
+source /home/yannherklotz/Github/FPGA-led-lights/pa.fromNcd.tcl
+# create_project -name FPGA-led-lights -dir "/home/yannherklotz/Github/FPGA-led-lights/planAhead_run_4" -part xc6slx9tqg144-2
+# set srcset [get_property srcset [current_run -impl]]
+# set_property design_mode GateLvl $srcset
+# set_property edif_top_file "/home/yannherklotz/Github/FPGA-led-lights/led.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {/home/yannherklotz/Github/FPGA-led-lights} }
+# set_property target_constrs_file "/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf" [current_fileset -constrset]
+Adding file '/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf' to fileset 'constrs_1'
+# add_files [list {/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf}] -fileset [get_property constrset [current_run]]
+# link_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to project part: xc6slx9tqg144-2
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Release 14.7 - ngc2edif P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Reading design led.ngc ...
+WARNING:NetListWriters:298 - No output is written to led.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file led.edif ...
+ngc2edif: Total memory usage is 103540 kilobytes
+
+Parsing EDIF File [./planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+Finished Parsing EDIF File [./planAhead_run_4/FPGA-led-lights.data/cache/led_ngc_cb841106.edif]
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockRegion.xml
+Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/ClockBuffers.xml
+Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
+Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/spartan6lx/xc6slx9/tqg144/Package.xml
+Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+Finished Parsing UCF File [/home/yannherklotz/Downloads/BPC3011-Papilio_Pro-general.ucf]
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 1 instances were transformed.
+  BUFGP => BUFGP (IBUF, BUFG): 1 instances
+
+Phase 0 | Netlist Checksum: 23693229
+link_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:07 . Memory (MB): peak = 2864.305 ; gain = 189.508
+# read_xdl -file "/home/yannherklotz/Github/FPGA-led-lights/led.ncd"
+Release 14.7 - xdl P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
+Loading device for application Rf_Device from file '6slx9.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
+   "led" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
+Successfully converted design '/home/yannherklotz/Github/FPGA-led-lights/led.ncd' to '/home/yannherklotz/Github/FPGA-led-lights/led.xdl'.
+INFO: [Designutils 20-669] Parsing Placement File : /home/yannherklotz/Github/FPGA-led-lights/led.ncd
+INFO: [Designutils 20-658] Finished Parsing Placement File : /home/yannherklotz/Github/FPGA-led-lights/led.ncd
+INFO: [Designutils 20-671] Placed 87 instances
+read_xdl: Time (s): cpu = 00:00:11 ; elapsed = 00:00:06 . Memory (MB): peak = 2864.305 ; gain = 0.000
+# if {[catch {read_twx -name results_1 -file "/home/yannherklotz/Github/FPGA-led-lights/led.twx"} eInfo]} {
+#    puts "WARNING: there was a problem importing \"/home/yannherklotz/Github/FPGA-led-lights/led.twx\": $eInfo"
+# }
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+MEvent. CASE!
+add wave clock enable
+invalid command name "add"
+ambiguous command name "add": add_cells_to_pblock add_files
+create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
+WARNING: [PlanAhead 12-584] No ports matched 'CLOCK_50'.
+invalid command name "create_clock"
+add
+invalid command name "add"
+ambiguous command name "add": add_cells_to_pblock add_files
+run
+invalid command name "run"
+exit
+ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
+INFO: [Common 17-206] Exiting PlanAhead at Tue Feb 21 21:53:15 2017...
+INFO: [Common 17-83] Releasing license: PlanAhead