diff options
Diffstat (limited to 'FPGA-led-lights.gise')
| -rw-r--r-- | FPGA-led-lights.gise | 151 |
1 files changed, 141 insertions, 10 deletions
diff --git a/FPGA-led-lights.gise b/FPGA-led-lights.gise index 481f264..d852a79 100644 --- a/FPGA-led-lights.gise +++ b/FPGA-led-lights.gise @@ -22,64 +22,195 @@ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FPGA-led-lights.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="led.bgn" xil_pn:subbranch="FPGAConfiguration"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="led.bit" xil_pn:subbranch="FPGAConfiguration"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="led.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="led.cmd_log"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="led.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="led.lso"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="led.ncd" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="led.ngc"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="led.ngd"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="led.ngr"/>
+ <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="led.pad"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="led.par" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="led.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="led.prj"/>
+ <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="led.ptwx"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="led.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="led.syr"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="led.twr" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="led.twx" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="led.unroutes" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="led.ut" xil_pn:subbranch="FPGAConfiguration"/>
+ <file xil_pn:fileType="FILE_XPI" xil_pn:name="led.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="led.xst"/>
+ <file xil_pn:fileType="FILE_HTML" xil_pn:name="led_envsettings.html"/>
+ <file xil_pn:fileType="FILE_NCD" xil_pn:name="led_guide.ncd" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="led_map.map" xil_pn:subbranch="Map"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="led_map.mrp" xil_pn:subbranch="Map"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="led_map.ncd" xil_pn:subbranch="Map"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="led_map.ngm" xil_pn:subbranch="Map"/>
+ <file xil_pn:fileType="FILE_XRPT" xil_pn:name="led_map.xrpt"/>
+ <file xil_pn:fileType="FILE_XRPT" xil_pn:name="led_ngdbuild.xrpt"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="led_pad.csv" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="led_pad.txt" xil_pn:subbranch="Par"/>
+ <file xil_pn:fileType="FILE_XRPT" xil_pn:name="led_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="led_summary.html"/>
+ <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="led_summary.xml"/>
+ <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="led_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="led_xst.xrpt"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_4"/>
+ <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
+ <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
- <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1487546128">
+ <transform xil_pn:end_ts="1487712773" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1487712773">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6442174705589123182" xil_pn:start_ts="1487546129">
+ <transform xil_pn:end_ts="1487712773" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="2687710351385008554" xil_pn:start_ts="1487712773">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1227048648073386772" xil_pn:start_ts="1487546129">
+ <transform xil_pn:end_ts="1487713076" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8564384985097914375" xil_pn:start_ts="1487713076">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1487546129">
+ <transform xil_pn:end_ts="1487712773" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1487712773">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="2590979178147000940" xil_pn:start_ts="1487546129">
+ <transform xil_pn:end_ts="1487712773" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="2590979178147000940" xil_pn:start_ts="1487712773">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="5199527252420087910" xil_pn:start_ts="1487546129">
+ <transform xil_pn:end_ts="1487712773" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1487712773">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1487546129" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-421007744913001546" xil_pn:start_ts="1487546129">
+ <transform xil_pn:end_ts="1487713076" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8229807836551992707" xil_pn:start_ts="1487713076">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1487546132" xil_pn:in_ck="131819641" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-9170951106228638093" xil_pn:start_ts="1487546129">
- <status xil_pn:value="FailedRun"/>
+ <transform xil_pn:end_ts="1487715017" xil_pn:in_ck="131819641" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="4753490412739147880" xil_pn:start_ts="1487715011">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="led.lso"/>
+ <outfile xil_pn:name="led.ngc"/>
+ <outfile xil_pn:name="led.ngr"/>
<outfile xil_pn:name="led.prj"/>
+ <outfile xil_pn:name="led.stx"/>
<outfile xil_pn:name="led.syr"/>
<outfile xil_pn:name="led.xst"/>
<outfile xil_pn:name="led_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
- <transform xil_pn:end_ts="1487546132" xil_pn:in_ck="8586762664122563020" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3734212952602903" xil_pn:start_ts="1487546132">
+ <transform xil_pn:end_ts="1487715399" xil_pn:in_ck="4834887014787387356" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3734212952602903" xil_pn:start_ts="1487715399">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1487715404" xil_pn:in_ck="-6554730637971917129" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-5807652207078553553" xil_pn:start_ts="1487715399">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="WarningsGenerated"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <outfile xil_pn:name="_ngo"/>
+ <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+ <outfile xil_pn:name="led.bld"/>
+ <outfile xil_pn:name="led.ngd"/>
+ <outfile xil_pn:name="led_ngdbuild.xrpt"/>
+ </transform>
+ <transform xil_pn:end_ts="1487715414" xil_pn:in_ck="-6554730637971917128" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1487715407">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
+ <outfile xil_pn:name="led.pcf"/>
+ <outfile xil_pn:name="led_map.map"/>
+ <outfile xil_pn:name="led_map.mrp"/>
+ <outfile xil_pn:name="led_map.ncd"/>
+ <outfile xil_pn:name="led_map.ngm"/>
+ <outfile xil_pn:name="led_map.xrpt"/>
+ <outfile xil_pn:name="led_summary.xml"/>
+ <outfile xil_pn:name="led_usage.xml"/>
+ </transform>
+ <transform xil_pn:end_ts="1487715423" xil_pn:in_ck="-8547227296926146095" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1487715414">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
+ <outfile xil_pn:name="led.ncd"/>
+ <outfile xil_pn:name="led.pad"/>
+ <outfile xil_pn:name="led.par"/>
+ <outfile xil_pn:name="led.ptwx"/>
+ <outfile xil_pn:name="led.unroutes"/>
+ <outfile xil_pn:name="led.xpi"/>
+ <outfile xil_pn:name="led_pad.csv"/>
+ <outfile xil_pn:name="led_pad.txt"/>
+ <outfile xil_pn:name="led_par.xrpt"/>
+ </transform>
+ <transform xil_pn:end_ts="1487715430" xil_pn:in_ck="143551583704" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="5341574683187206424" xil_pn:start_ts="1487715423">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+ <outfile xil_pn:name="led.bgn"/>
+ <outfile xil_pn:name="led.bit"/>
+ <outfile xil_pn:name="led.drc"/>
+ <outfile xil_pn:name="led.ut"/>
+ <outfile xil_pn:name="usage_statistics_webtalk.html"/>
+ <outfile xil_pn:name="webtalk.log"/>
+ <outfile xil_pn:name="webtalk_pn.xml"/>
+ </transform>
+ <transform xil_pn:end_ts="1487713792" xil_pn:in_ck="-3553499765603855836" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1487713790">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="InputAdded"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="InputRemoved"/>
+ </transform>
+ <transform xil_pn:end_ts="1487715423" xil_pn:in_ck="-6554730637971917260" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1487715419">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
+ <outfile xil_pn:name="led.twr"/>
+ <outfile xil_pn:name="led.twx"/>
+ </transform>
+ <transform xil_pn:end_ts="1487713747" xil_pn:in_ck="-3553499765603855704" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1487713741">
+ <status xil_pn:value="FailedRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="InputAdded"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="InputRemoved"/>
</transform>
</transforms>
|