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Diffstat (limited to 'led_map.map')
| -rw-r--r-- | led_map.map | 146 |
1 files changed, 146 insertions, 0 deletions
diff --git a/led_map.map b/led_map.map new file mode 100644 index 0000000..050a07f --- /dev/null +++ b/led_map.map @@ -0,0 +1,146 @@ +Release 14.7 Map P.20131013 (lin64) +Xilinx Map Application Log File for Design 'led' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol +high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off +-pr off -lc off -power off -o led_map.ncd led.ngd led.pcf +Target Device : xc6slx9 +Target Package : tqg144 +Target Speed : -2 +Mapper Version : spartan6 -- $Revision: 1.55 $ +Mapped Date : Tue Feb 21 22:16:49 2017 + +Mapping design into LUTs... +Running directed packing... +Running delay-based LUT packing... +Updating timing models... +INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report + (.mrp). +Running timing-driven placement... +Total REAL time at the beginning of Placer: 3 secs +Total CPU time at the beginning of Placer: 3 secs + +Phase 1.1 Initial Placement Analysis +Phase 1.1 Initial Placement Analysis (Checksum:184813e3) REAL time: 3 secs + +Phase 2.7 Design Feasibility Check +Phase 2.7 Design Feasibility Check (Checksum:184813e3) REAL time: 3 secs + +Phase 3.31 Local Placement Optimization +Phase 3.31 Local Placement Optimization (Checksum:184813e3) REAL time: 3 secs + +Phase 4.2 Initial Placement for Architecture Specific Features + +Phase 4.2 Initial Placement for Architecture Specific Features +(Checksum:e8c062d1) REAL time: 4 secs + +Phase 5.36 Local Placement Optimization +Phase 5.36 Local Placement Optimization (Checksum:e8c062d1) REAL time: 4 secs + +Phase 6.30 Global Clock Region Assignment +Phase 6.30 Global Clock Region Assignment (Checksum:e8c062d1) REAL time: 4 secs + +Phase 7.3 Local Placement Optimization +Phase 7.3 Local Placement Optimization (Checksum:e8c062d1) REAL time: 4 secs + +Phase 8.5 Local Placement Optimization +Phase 8.5 Local Placement Optimization (Checksum:e8c062d1) REAL time: 4 secs + +Phase 9.8 Global Placement +.. +.. +Phase 9.8 Global Placement (Checksum:973ccb49) REAL time: 4 secs + +Phase 10.5 Local Placement Optimization +Phase 10.5 Local Placement Optimization (Checksum:973ccb49) REAL time: 4 secs + +Phase 11.18 Placement Optimization +Phase 11.18 Placement Optimization (Checksum:ed34dee1) REAL time: 4 secs + +Phase 12.5 Local Placement Optimization +Phase 12.5 Local Placement Optimization (Checksum:ed34dee1) REAL time: 4 secs + +Phase 13.34 Placement Validation +Phase 13.34 Placement Validation (Checksum:ed34dee1) REAL time: 4 secs + +Total REAL time to Placer completion: 4 secs +Total CPU time to Placer completion: 4 secs +Running post-placement packing... +Writing output files... + +Design Summary +-------------- + +Design Summary: +Number of errors: 0 +Number of warnings: 0 +Slice Logic Utilization: + Number of Slice Registers: 25 out of 11,440 1% + Number used as Flip Flops: 25 + Number used as Latches: 0 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 0 + Number of Slice LUTs: 57 out of 5,720 1% + Number used as logic: 57 out of 5,720 1% + Number using O6 output only: 34 + Number using O5 output only: 1 + Number using O5 and O6: 22 + Number used as ROM: 0 + Number used as Memory: 0 out of 1,440 0% + +Slice Logic Distribution: + Number of occupied Slices: 15 out of 1,430 1% + Number of MUXCYs used: 24 out of 2,860 1% + Number of LUT Flip Flop pairs used: 57 + Number with an unused Flip Flop: 32 out of 57 56% + Number with an unused LUT: 0 out of 57 0% + Number of fully used LUT-FF pairs: 25 out of 57 43% + Number of unique control sets: 1 + Number of slice register sites lost + to control set restrictions: 7 out of 11,440 1% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + +IO Utilization: + Number of bonded IOBs: 2 out of 102 1% + Number of LOCed IOBs: 2 out of 2 100% + +Specific Feature Utilization: + Number of RAMB16BWERs: 0 out of 32 0% + Number of RAMB8BWERs: 0 out of 64 0% + Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% + Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% + Number of BUFG/BUFGMUXs: 1 out of 16 6% + Number used as BUFGs: 1 + Number used as BUFGMUX: 0 + Number of DCM/DCM_CLKGENs: 0 out of 4 0% + Number of ILOGIC2/ISERDES2s: 0 out of 200 0% + Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0% + Number of OLOGIC2/OSERDES2s: 0 out of 200 0% + Number of BSCANs: 0 out of 4 0% + Number of BUFHs: 0 out of 128 0% + Number of BUFPLLs: 0 out of 8 0% + Number of BUFPLL_MCBs: 0 out of 4 0% + Number of DSP48A1s: 0 out of 16 0% + Number of ICAPs: 0 out of 1 0% + Number of MCBs: 0 out of 2 0% + Number of PCILOGICSEs: 0 out of 2 0% + Number of PLL_ADVs: 0 out of 2 0% + Number of PMVs: 0 out of 1 0% + Number of STARTUPs: 0 out of 1 0% + Number of SUSPEND_SYNCs: 0 out of 1 0% + +Average Fanout of Non-Clock Nets: 3.24 + +Peak Memory Usage: 654 MB +Total REAL time to MAP completion: 4 secs +Total CPU time to MAP completion: 4 secs + +Mapping completed. +See MAP report file "led_map.mrp" for details. |