diff options
Diffstat (limited to 'planAhead_run_1/FPGA-led-lights.data/wt/webtalk_pa.xml')
| -rw-r--r-- | planAhead_run_1/FPGA-led-lights.data/wt/webtalk_pa.xml | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/planAhead_run_1/FPGA-led-lights.data/wt/webtalk_pa.xml b/planAhead_run_1/FPGA-led-lights.data/wt/webtalk_pa.xml new file mode 100644 index 0000000..828cdf0 --- /dev/null +++ b/planAhead_run_1/FPGA-led-lights.data/wt/webtalk_pa.xml @@ -0,0 +1,27 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<document> +<!--The data in this file is primarily intended for consumption by Xilinx tools. +The structure and the elements are likely to change over the next few releases. +This means code written to parse this file will need to be revisited each subsequent release.--> +<application name="pa" timeStamp="Tue Feb 21 20:21:00 2017"> +<section name="Project Information" visible="false"> +<property name="ProjectID" value="5162b49b77234a039edc109f3f038375" type="ProjectID"/> +<property name="ProjectIteration" value="1" type="ProjectIteration"/> +</section> +<section name="PlanAhead Usage" visible="true"> +<item name="Project Data"> +<property name="SrcSetCount" value="1" type="SrcSetCount"/> +<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/> +<property name="DesignMode" value="RTL" type="DesignMode"/> +<property name="SynthesisStrategy" value="PlanAhead Defaults" type="SynthesisStrategy"/> +<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/> +</item> +<item name="Other"> +<property name="GuiMode" value="0" type="GuiMode"/> +<property name="BatchMode" value="0" type="BatchMode"/> +<property name="TclMode" value="0" type="TclMode"/> +<property name="ISEMode" value="1" type="ISEMode"/> +</item> +</section> +</application> +</document> |