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-rw-r--r--planAhead_run_2/FPGA-led-lights.data/runs/impl_1.psg20
-rw-r--r--planAhead_run_2/FPGA-led-lights.data/runs/runs.xml5
2 files changed, 25 insertions, 0 deletions
diff --git a/planAhead_run_2/FPGA-led-lights.data/runs/impl_1.psg b/planAhead_run_2/FPGA-led-lights.data/runs/impl_1.psg
new file mode 100644
index 0000000..147f3a9
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/runs/impl_1.psg
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+ <StratHandle Name="ISE Defaults" Flow="ISE14">
+ <Desc>ISE Defaults, including packing registers in IOs off</Desc>
+ </StratHandle>
+ <Step Id="ngdbuild">
+ </Step>
+ <Step Id="map">
+ <Option Id="FFPackEnum">3</Option>
+ </Step>
+ <Step Id="par">
+ </Step>
+ <Step Id="trce">
+ </Step>
+ <Step Id="xdl">
+ </Step>
+ <Step Id="bitgen">
+ </Step>
+</Strategy>
+
diff --git a/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml b/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml
new file mode 100644
index 0000000..fe0b8b1
--- /dev/null
+++ b/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc3s250evq100-4" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/>
+</Runs>
+