diff options
Diffstat (limited to 'planAhead_run_2/FPGA-led-lights.data')
13 files changed, 1294 insertions, 0 deletions
diff --git a/planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif b/planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif new file mode 100644 index 0000000..ad5dec0 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/cache/led_ngc_cb841106.edif @@ -0,0 +1,1149 @@ +(edif led + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2017 2 21 20 23 20) + (program "Xilinx ngc2edif" (version "P.20131013")) + (author "Xilinx. Inc ") + (comment "This EDIF netlist is to be used within supported synthesis tools") + (comment "for determining resource/timing estimates of the design component") + (comment "represented by this netlist.") + (comment "Command line: -mdp2sp -w -secure led.ngc led.edif "))) + (external UNISIMS + (edifLevel 0) + (technology (numberDefinition)) + (cell GND + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell VCC + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port P + (direction OUTPUT) + ) + ) + ) + ) + (cell FDE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDS + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDR + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell XORCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port LI + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT1 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell BUFGP + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell INV + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT4_L + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port LO + (direction OUTPUT) + ) + ) + ) + ) + ) + + (library led_lib + (edifLevel 0) + (technology (numberDefinition)) + (cell led + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CLK + (direction INPUT) + ) + (port A0 + (direction OUTPUT) + ) + (designator "xc3s250e-4-vq100") + (property TYPE (string "led") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 0) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "led_led") (owner "Xilinx")) + ) + (contents + (instance XST_GND + (viewRef view_1 (cellRef GND (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance XST_VCC + (viewRef view_1 (cellRef VCC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename A0_renamed_0 "A0") + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_1 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_0 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_2 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_3 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_4 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_5 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_6 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_7 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_8 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_9 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_10 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_11 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_12 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_13 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance count_14 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance count_15 + (viewRef view_1 (cellRef FDS (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_0___renamed_1 "Mcount_count_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_0__ "Mcount_count_xor<0>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_1___renamed_2 "Mcount_count_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_1__ "Mcount_count_xor<1>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_2___renamed_3 "Mcount_count_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_2__ "Mcount_count_xor<2>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_3___renamed_4 "Mcount_count_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_3__ "Mcount_count_xor<3>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_4___renamed_5 "Mcount_count_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_4__ "Mcount_count_xor<4>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_5___renamed_6 "Mcount_count_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_5__ "Mcount_count_xor<5>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_6___renamed_7 "Mcount_count_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_6__ "Mcount_count_xor<6>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_7___renamed_8 "Mcount_count_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_7__ "Mcount_count_xor<7>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_8___renamed_9 "Mcount_count_cy<8>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_8__ "Mcount_count_xor<8>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_9___renamed_10 "Mcount_count_cy<9>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_9__ "Mcount_count_xor<9>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_10___renamed_11 "Mcount_count_cy<10>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_10__ "Mcount_count_xor<10>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_11___renamed_12 "Mcount_count_cy<11>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_11__ "Mcount_count_xor<11>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_12___renamed_13 "Mcount_count_cy<12>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_12__ "Mcount_count_xor<12>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_13___renamed_14 "Mcount_count_cy<13>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_13__ "Mcount_count_xor<13>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_14___renamed_15 "Mcount_count_cy<14>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_14__ "Mcount_count_xor<14>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_15__ "Mcount_count_xor<15>") + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename A0_cmp_eq000025_renamed_16 "A0_cmp_eq000025") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001") (owner "Xilinx")) + ) + (instance (rename A0_cmp_eq000049_renamed_17 "A0_cmp_eq000049") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001") (owner "Xilinx")) + ) + (instance (rename A0_cmp_eq000062_renamed_18 "A0_cmp_eq000062") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001") (owner "Xilinx")) + ) + (instance A0_cmp_eq000076 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "8000") (owner "Xilinx")) + ) + (instance (rename A0_OBUF_renamed_19 "A0_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_1__rt_renamed_20 "Mcount_count_cy<1>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_2__rt_renamed_21 "Mcount_count_cy<2>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_3__rt_renamed_22 "Mcount_count_cy<3>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_4__rt_renamed_23 "Mcount_count_cy<4>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_5__rt_renamed_24 "Mcount_count_cy<5>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_6__rt_renamed_25 "Mcount_count_cy<6>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_7__rt_renamed_26 "Mcount_count_cy<7>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_8__rt_renamed_27 "Mcount_count_cy<8>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_9__rt_renamed_28 "Mcount_count_cy<9>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_10__rt_renamed_29 "Mcount_count_cy<10>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_11__rt_renamed_30 "Mcount_count_cy<11>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_12__rt_renamed_31 "Mcount_count_cy<12>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_13__rt_renamed_32 "Mcount_count_cy<13>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_cy_14__rt_renamed_33 "Mcount_count_cy<14>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename Mcount_count_xor_15__rt_renamed_34 "Mcount_count_xor<15>_rt") + (viewRef view_1 (cellRef LUT1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "2") (owner "Xilinx")) + ) + (instance (rename CLK_BUFGP_renamed_35 "CLK_BUFGP") + (viewRef view_1 (cellRef BUFGP (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename Mcount_count_lut_0__INV_0 "Mcount_count_lut<0>_INV_0") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance A0_not00031_INV_0 + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename A0_cmp_eq000012_renamed_36 "A0_cmp_eq000012") + (viewRef view_1 (cellRef LUT4_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0001") (owner "Xilinx")) + ) + (net A0 + (joined + (portRef A0) + (portRef O (instanceRef A0_OBUF_renamed_19)) + ) + ) + (net A0_OBUF + (joined + (portRef Q (instanceRef A0_renamed_0)) + (portRef I (instanceRef A0_OBUF_renamed_19)) + (portRef I (instanceRef A0_not00031_INV_0)) + ) + ) + (net A0_cmp_eq000012 + (joined + (portRef I0 (instanceRef A0_cmp_eq000076)) + (portRef LO (instanceRef A0_cmp_eq000012_renamed_36)) + ) + ) + (net A0_cmp_eq000025 + (joined + (portRef O (instanceRef A0_cmp_eq000025_renamed_16)) + (portRef I1 (instanceRef A0_cmp_eq000076)) + ) + ) + (net A0_cmp_eq000049 + (joined + (portRef O (instanceRef A0_cmp_eq000049_renamed_17)) + (portRef I2 (instanceRef A0_cmp_eq000076)) + ) + ) + (net A0_cmp_eq000062 + (joined + (portRef O (instanceRef A0_cmp_eq000062_renamed_18)) + (portRef I3 (instanceRef A0_cmp_eq000076)) + ) + ) + (net A0_not0002_inv + (joined + (portRef CE (instanceRef A0_renamed_0)) + (portRef S (instanceRef count_1)) + (portRef S (instanceRef count_0)) + (portRef S (instanceRef count_2)) + (portRef S (instanceRef count_3)) + (portRef R (instanceRef count_4)) + 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0000000..147f3a9 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/runs/impl_1.psg @@ -0,0 +1,20 @@ +<?xml version="1.0"?> +<Strategy Version="1" Minor="2"> + <StratHandle Name="ISE Defaults" Flow="ISE14"> + <Desc>ISE Defaults, including packing registers in IOs off</Desc> + </StratHandle> + <Step Id="ngdbuild"> + </Step> + <Step Id="map"> + <Option Id="FFPackEnum">3</Option> + </Step> + <Step Id="par"> + </Step> + <Step Id="trce"> + </Step> + <Step Id="xdl"> + </Step> + <Step Id="bitgen"> + </Step> +</Strategy> + diff --git a/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml b/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml new file mode 100644 index 0000000..fe0b8b1 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/runs/runs.xml @@ -0,0 +1,5 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="8"> + <Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc3s250evq100-4" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/> +</Runs> + diff --git a/planAhead_run_2/FPGA-led-lights.data/sim_1/fileset.xml b/planAhead_run_2/FPGA-led-lights.data/sim_1/fileset.xml new file mode 100644 index 0000000..65babe3 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/sim_1/fileset.xml @@ -0,0 +1,10 @@ +<?xml version="1.0" encoding="UTF-8"?> +<DARoots Version="1" Minor="26"> + <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1"> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="SrcSet" Val="sources_1"/> + </Config> + </FileSet> +</DARoots> diff --git a/planAhead_run_2/FPGA-led-lights.data/sources_1/chipscope.xml b/planAhead_run_2/FPGA-led-lights.data/sources_1/chipscope.xml new file mode 100644 index 0000000..3fd9702 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/sources_1/chipscope.xml @@ -0,0 +1,6 @@ +<?xml version="1.0"?> +<ChipScope Version="1" Minor="3"> + <UnassignedNets> + </UnassignedNets> +</ChipScope> + diff --git a/planAhead_run_2/FPGA-led-lights.data/sources_1/fileset.xml b/planAhead_run_2/FPGA-led-lights.data/sources_1/fileset.xml new file mode 100644 index 0000000..9fa644d --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/sources_1/fileset.xml @@ -0,0 +1,24 @@ +<?xml version="1.0" encoding="UTF-8"?> +<DARoots Version="1" Minor="26"> + <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> + <Filter Type="EDIFSrcs"/> + <File Path="$PPRDIR/../led.ngc"> + <FileInfo> + <Attr Name="UsedInSynthesis" Val="1"/> + <Attr Name="UsedInImplementation" Val="1"/> + </FileInfo> + </File> + <File Path="$PDATADIR/sources_1/ports.xml"> + <FileInfo SFType="PortsDb"/> + </File> + <File Path="$PDATADIR/sources_1/chipscope.xml"> + <FileInfo SFType="ChipscopeDb"/> + </File> + <Config> + <Option Name="DesignMode" Val="GateLvl"/> + <Option Name="GateLvlMode" Val="EDIF"/> + <Option Name="TopFile" Val="$PPRDIR/../led.ngc"/> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> +</DARoots> diff --git a/planAhead_run_2/FPGA-led-lights.data/sources_1/ports.xml b/planAhead_run_2/FPGA-led-lights.data/sources_1/ports.xml new file mode 100644 index 0000000..6edcb86 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/sources_1/ports.xml @@ -0,0 +1,8 @@ +<?xml version="1.0"?> +<Interface Version="1" Minor="1"> + <Ifc Id="ROOT" Top="1"> + <Port Id="CLK" Dir="IN"/> + <Port Id="A0" Dir="OUT"/> + </Ifc> +</Interface> + diff --git a/planAhead_run_2/FPGA-led-lights.data/wt/java_command_handlers.wdf b/planAhead_run_2/FPGA-led-lights.data/wt/java_command_handlers.wdf new file mode 100644 index 0000000..9880428 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/wt/java_command_handlers.wdf @@ -0,0 +1,3 @@ +version:1 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766564657369676e:31:00:00 +eof:3611541694 diff --git a/planAhead_run_2/FPGA-led-lights.data/wt/project.wpc b/planAhead_run_2/FPGA-led-lights.data/wt/project.wpc new file mode 100644 index 0000000..5fed558 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/wt/project.wpc @@ -0,0 +1,4 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +6d6f64655f636f756e7465727c4953454d6f6465:1 +eof: diff --git a/planAhead_run_2/FPGA-led-lights.data/wt/webtalk_pa.xml b/planAhead_run_2/FPGA-led-lights.data/wt/webtalk_pa.xml new file mode 100644 index 0000000..8f356a2 --- /dev/null +++ b/planAhead_run_2/FPGA-led-lights.data/wt/webtalk_pa.xml @@ -0,0 +1,29 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<document> +<!--The data in this file is primarily intended for consumption by Xilinx tools. +The structure and the elements are likely to change over the next few releases. +This means code written to parse this file will need to be revisited each subsequent release.--> +<application name="pa" timeStamp="Tue Feb 21 20:24:50 2017"> +<section name="Project Information" visible="false"> +<property name="ProjectID" value="a3587ea880e14b0e9bda22648980fcfc" type="ProjectID"/> +<property name="ProjectIteration" value="1" type="ProjectIteration"/> +</section> +<section name="PlanAhead Usage" visible="true"> +<item name="Project Data"> +<property name="SrcSetCount" value="1" type="SrcSetCount"/> +<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/> +<property name="DesignMode" value="GateLvl" type="DesignMode"/> +<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/> +</item> +<item name="Java Command Handlers"> +<property name="SaveDesign" value="1" type="JavaHandler"/> +</item> +<item name="Other"> +<property name="GuiMode" value="0" type="GuiMode"/> +<property name="BatchMode" value="0" type="BatchMode"/> +<property name="TclMode" value="0" type="TclMode"/> +<property name="ISEMode" value="3" type="ISEMode"/> +</item> +</section> +</application> +</document> |